Design Example - PMA Controls Reconfiguration - Stratix V GX

Design Example - PMA Controls Reconfiguration - Stratix V GX

External Links

Altera Transceiver PHY IP Core User Guide

Altera Stratix V Device Documentation

Altera Avalon Memory-Mapped Interface Specification (PDF)

Design File

for Quartus II v11.0

Altera Stratix V PMA Controls Reconfiguration Design File v11.0 (ZIP)

for Quartus II v13.1

Altera Stratix V PMA Controls Reconfiguration Design File v13.1 (ZIP)

Design Specifications

The table below lists the specifications for this design:

Attribute	Specification
Device Family	Stratix V GX
FPGA	5SGXMA7K2F40C2
Quartus version	QuartusII v11.0, b157
Modelsim version	Modelsim SE v6.6d
Datarate	3.125Gbps
Data pattern	PRBS 23
Number of channels	1
IP used	Custom PHY IP, Transceiver Reconfiguration Controller

The table below lists the specifications for the design for Quartus II V13.1 b162:

Attribute	Specification
Device Family	Stratix V GX
FPGA	5SGXMA7K2F40C2
Quartus version	QuartusII v13.1, b162
Modelsim version	Modelsim SE v10.0d
Datarate	3.125Gbps
Data pattern	PRBS 23
Number of channels	1
IP used	Custom PHY IP, Transceiver Reconfiguration Controller

Design Overview

This design example dynamically reconfigures transmitter VOD, pre-emphasis, receiver DC gain, and equalization for a Stratix V transceiver link implemented using a Custom PHY IP. The purpose of this design is to show you how to connect the transceiver reconfiguration controller to the PHY IP and reconfigure the PMA controls through the Avalon® memory-mapped (Avalon-MM) interface of the controller. The Avalon-MM interface of the controller is called the Reconfiguration Management Interface. This example creates four 3125 transceiver links using a Custom PHY IP, an example top-level file (top.sv), and a test bench (top_tb.sv). These files will be used to demonstrate the PMA controls reconfiguration feature in Stratix V devices.

This design focuses only on dynamic reconfiguration and not the Custom PHY IP functionality.

Figure 1 shows a high-level block diagram of this design

f/f4/Custom_block.JPG ( Custom block.JPG - click here to view image )

Block Diagram Details

This design implements the following blocks:

Custom PHY IP
Transceiver Reconfiguration Controller
PRBS Generator
PRBS Checker
Avalon Memory-Mapped (MM) Master

Custom PHY IP— The Custom PHY IP instantiates the Stratix V transceivers in custom configurations that use standard PCS and word aligner. This file is called top_custom.v in the reference design.

For implementation details, refer to the Custom PHY IP Core chapter in the Altera Transceiver PHY IP Core User Guide.

Transceiver Reconfiguration Controller—This file is called top_reconfig.v . It instantiates the Reconfig IP or the transceiver reconfiguration controller.

For implementation details, refer to the Transceiver Reconfiguration Controller chapter of the Altera Transceiver PHY IP Core User Guide.

Avalon-MM Master—This file is user created but conforms to Altera standard specification rules ( Avalon Interface Specifications).This file is called mgmt_master.sv and contains the following components:

mgmt_master.sv—the top-level wrapper that initializes ROM
mgmt_master_cpu.sv—the file containing the actual controller state machine
mgmt_commands_hv.sv—the package file that contains low-level parameters and command functions
mgmt_functions_h.sv—the package file that defines high-level functions called by the user program
mgmt_program.sv—the package file that contains the user’s program

User Created Logic—The following blocks are user created in this design:

GXB State Machine—The GXB state machine controls the sequence of events in design. It contains counters that monitor the three phases: reset phase, init phase, and data phase. Each phase must be completed before the next phase can begin. The state machine sends a control signal to the 2:1 MUX that identifies which phase is currently active for the Custom PHY IP.
Data Processing Unit—The data processing unit sends control signals to the sync generator and the PRBS generator. It selects the data from the sync generator during the init phase, and the data from the PRBS generator during the data phase. The data processing unit is called datagen_controller.v in the design.
Sync Generator—The sync generator begins operating in the init phase, after the tx_ready and rx_ready output signals of the Custom PHY IP are asserted. It transmits 8'hBCs into the four transmitter lanes of the Custom PHY IP. This ensures that the four receiver links are word aligned. The sync generator is called syncgen_16bit_1lane.v in this design.The syncgen_16bit_4lanes.v instantiates the sync generator four times for the four transceiver lanes.
PRBS Generator—The PRBS generator begins operating in the data phase, after the rx_syncstatus output signal of the Custom PHY IP is asserted. It generates the payload (PRBS23 data) for the Custom PHY IP. It is called prbs_generator.v in this design.
PRBS Checker—The PRBS checker is called prbs_checker.v in the design. The prbs_checker_x4.v file instantiates the checker four times for the four receiver lanes. It verifies that the data transmitted into the transmitter is received correctly at the output of the receiver.

Design Implementation Details

This section goes over the steps to create this example design

Set up the transceiver channels in the Custom PHY IP

- Use the MegaWizard™ Plug-In Manager to instantiate the Custom PHY IP.

- To open the MegaWizard Plug-In Manager, click Installed Plug-Ins > Interfaces >Transceiver PHY > Custom Phy IP v11.0.

Set up the transceiver reconfiguration controller/Reconfig IP

- Use the MegaWizard Plug-In Manager to instantiate the controller.

- To open the MegaWizard Plug-In Manager, click Installed Plug-Ins > Interfaces >Transceiver PHY > Transceiver Reconfiguration Controller.

Connect the transceiver channels to the Reconfig IP
Create an Avalon-MM master user logic

- Use one of the following options to create a synthesizable Avalon-MM master:

a) Write your own state machine to interact with the Avalon-MM interface

b) Use the NIOS® II processor from the Qsys system to send reads and writes to the Avalon-MM interface

c) Use your own external processor and create a bridge to the Avalon-MM interface.

- The design gives an example of a synthesizable Avalon-MM Master.

- Use the Avalon-MM master to communicate with the controller’s reconfiguration management interface.

- The only file that you must change in this design is master_program.sv.

- Regardless of which option you choose to create the master, you must follow the Avalon specifications described in the Avalon Interface Specifications.

Connect the remaining user-created logic
Create a Quartus Project File (.qpf) and compile the design
Simulate the design

- The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl

Compilation in Quartus

1) Download and unzip the zip files linked above into a folder to be used as the download directory.

2) Open the project file (.qpf) by going to File > Open Project and navigating to <download_directory>\SV_RECONFIG_PMA_CONTROL\source. Open top.qpf.

3) Use the Megawizard Plug-in Manager to generate Altera Generated IP (labeled in figure 1-1)

Before compiling you must regenerate the Altera generated IP using the Megawizard. You will perform this step twice - once for the top_custom.v and once for the top_reconfig.v. Open MegaWizard Plug-In Manager and choose edit a variation.

Select the IP you want to edit and generate (The .v file will be located in your project directory).
If your license for ModelSim can not support multiple HDL languages then chose verilog as output file type (The default settings will work for this example).
Select the options for the IP you want to generate (The default settings will work for this example), and click Finish.

After the previous steps have been completed, you can compile the entire design by going to Processing > Start > Start Analysis and Synthesis.

4) During compilation you can expect following critical warnings

Critical Warning (169085): No exact pin location assignment(s) for 12 pins of 12 total pins.
Critical Warning: Timing requirements not met.
Critical Warning: Synopsys Design Constraints File file not found: 'top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning: Ignored Power-Up Level option on the registers

Update History

Initial Release - May 05 2011

Key Words

Stratix V, Custom PHY IP, Tranceiver Reconfiguration Controller