Altera Transceiver PHY IP Core User Guide
Altera Stratix V Device Documentation
Altera Avalon Memory-Mapped Interface Specification (PDF)
for Quartus II v11.0
Altera Stratix V PMA Controls Reconfiguration Design File v11.0 (ZIP)
for Quartus II v13.1
The table below lists the specifications for this design:
Attribute | Specification |
Device Family | Stratix V GX |
FPGA | 5SGXMA7K2F40C2 |
Quartus version | QuartusII v11.0, b157 |
Modelsim version | Modelsim SE v6.6d |
Datarate | 3.125Gbps |
Data pattern | PRBS 23 |
Number of channels | 1 |
IP used | Custom PHY IP, Transceiver Reconfiguration Controller |
The table below lists the specifications for the design for Quartus II V13.1 b162:
Attribute | Specification |
Device Family | Stratix V GX |
FPGA | 5SGXMA7K2F40C2 |
Quartus version | QuartusII v13.1, b162 |
Modelsim version | Modelsim SE v10.0d |
Datarate | 3.125Gbps |
Data pattern | PRBS 23 |
Number of channels | 1 |
IP used | Custom PHY IP, Transceiver Reconfiguration Controller |
This design example dynamically reconfigures transmitter VOD, pre-emphasis, receiver DC gain, and equalization for a Stratix V transceiver link implemented using a Custom PHY IP. The purpose of this design is to show you how to connect the transceiver reconfiguration controller to the PHY IP and reconfigure the PMA controls through the Avalon® memory-mapped (Avalon-MM) interface of the controller. The Avalon-MM interface of the controller is called the Reconfiguration Management Interface. This example creates four 3125 transceiver links using a Custom PHY IP, an example top-level file (top.sv), and a test bench (top_tb.sv). These files will be used to demonstrate the PMA controls reconfiguration feature in Stratix V devices.
This design focuses only on dynamic reconfiguration and not the Custom PHY IP functionality.
Figure 1 shows a high-level block diagram of this design
This design implements the following blocks:
Custom PHY IP— The Custom PHY IP instantiates the Stratix V transceivers in custom configurations that use standard PCS and word aligner. This file is called top_custom.v in the reference design.
For implementation details, refer to the Custom PHY IP Core chapter in the Altera Transceiver PHY IP Core User Guide.
Transceiver Reconfiguration Controller—This file is called top_reconfig.v . It instantiates the Reconfig IP or the transceiver reconfiguration controller.
For implementation details, refer to the Transceiver Reconfiguration Controller chapter of the Altera Transceiver PHY IP Core User Guide.
Avalon-MM Master—This file is user created but conforms to Altera standard specification rules ( Avalon Interface Specifications).This file is called mgmt_master.sv and contains the following components:
User Created Logic—The following blocks are user created in this design:
This section goes over the steps to create this example design
- Use the MegaWizard™ Plug-In Manager to instantiate the Custom PHY IP.
- To open the MegaWizard Plug-In Manager, click Installed Plug-Ins > Interfaces >Transceiver PHY > Custom Phy IP v11.0.
- Use the MegaWizard Plug-In Manager to instantiate the controller.
- To open the MegaWizard Plug-In Manager, click Installed Plug-Ins > Interfaces >Transceiver PHY > Transceiver Reconfiguration Controller.
- Use one of the following options to create a synthesizable Avalon-MM master:
a) Write your own state machine to interact with the Avalon-MM interface
b) Use the NIOS® II processor from the Qsys system to send reads and writes to the Avalon-MM interface
c) Use your own external processor and create a bridge to the Avalon-MM interface.
- The design gives an example of a synthesizable Avalon-MM Master.
- Use the Avalon-MM master to communicate with the controller’s reconfiguration management interface.
- The only file that you must change in this design is master_program.sv.
- Regardless of which option you choose to create the master, you must follow the Avalon specifications described in the Avalon Interface Specifications.
- The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl
1) Download and unzip the zip files linked above into a folder to be used as the download directory.
2) Open the project file (.qpf) by going to File > Open Project and navigating to <download_directory>\SV_RECONFIG_PMA_CONTROL\source. Open top.qpf.
3) Use the Megawizard Plug-in Manager to generate Altera Generated IP (labeled in figure 1-1)
Before compiling you must regenerate the Altera generated IP using the Megawizard. You will perform this step twice - once for the top_custom.v and once for the top_reconfig.v. Open MegaWizard Plug-In Manager and choose edit a variation.
After the previous steps have been completed, you can compile the entire design by going to Processing > Start > Start Analysis and Synthesis.
4) During compilation you can expect following critical warnings
Stratix V, Custom PHY IP, Tranceiver Reconfiguration Controller
For more complete information about compiler optimizations, see our Optimization Notice.