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Design Example - SIV ALTMEMPHY DDR3 400MHz - 3 Shared Controllers

Design Example - SIV ALTMEMPHY DDR3 400MHz - 3 Shared Controllers



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Last Major Update

Initial Release - November 11th 2010 - SIV ALTMEMPHY DDR3 400MHz, two x16 and one x32 shared interfaces, QuartusII v8.1

Design Overview

This design features 3 DDR3 controllers on the top edge (two x16 interfaces & one x32 interface) operating at 400-MHz/800-Mbps. This example design uses the ALTMEMPHY megafunction-based DDR3 SDRAM High Performance Controller MegaCore. In addition, one DLL & 3 static PLL clocks are shared across all controllers. This timing closed design can used as an example showing feasibility for 3 controllers on one side of device with DLL/PLL sharing. For more information, please refer to the Altera External Memory Interface Handbook.


Design Specifications

Design files are located here File:Design Example SIV ALTMEMPHY DDR3 400MHz Three Shared Controllers FILES.zip

The table below lists the specifications for this design:  

AttributeSpecification
Quartus versionQuartusII v8.1
FPGAEP4SGX230KF40C2
KitNA
Memory deviceDDR3
Memory speed400MHz
Memory topologyTwo x16 and one x32 shared interfaces
IP usedALTMEMPHY

 

Notes/Comments



Update History

  1. Initial Release - November 11th 2010 - SIV ALTMEMPHY DDR3 400MHz, two x16 and one x32 shared interfaces, QuartusII v8.1

See Also

  1.   List of designs using Altera External Memory IP

 

External Links

  1. Altera's External Memory Interface Solutions Center
  2. Altera's External Memory Interface Handbook

 

Key Words

ALTMEMPHY, DDR3, Design Example, External Memory, Multiple Controllers, Shared, Stratix IV, SI 

 

 

  

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Version history
Revision #:
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Last update:
‎06-27-2019 03:58 PM
Updated by:
 
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