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Design Example - SIV ALTMEMPHY DDR3 400MHz - Four Controllers

Design Example - SIV ALTMEMPHY DDR3 400MHz - Four Controllers

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Last Major Update

Initial Release - November 11th 2010 - SIV ALTMEMPHY DDR3 400MHz, four x72 independent interfaces, QuartusII v8.0SP1

Design Overview

This design shows 4 x72 DDR3 SDRAM DIMM high-performance controllers fitting in a EP4SGX530 F1932 package. No resources are shared in this design. This design is to show that four DIMMs can fit in one FPGA and to also show how to stamp out four exact controllers with one ALTMEMPHY instantiation. The SDC and report_timing.tcl will be able to constrain and report the timing result for all four controllers without additional work.

This design has not been simulated or tested on the board.

Design Specifications

Design files are located here.

The table below lists the specifications for this design:  

Quartus versionQuartusII v8.0SP1
Memory deviceDDR3
Memory speed400MHz
Memory topologyFour x72 independent interfaces



Update History

  1. Initial Release - November 11th 2010 - SIV ALTMEMPHY DDR3 400MHz, four x72 independent interfaces, QuartusII v8.0SP1

See Also

  1.   List of designs using Altera External Memory IP


External Links

  1. Altera's External Memory Interface Solutions Center
  2. Altera's External Memory Interface Handbook


Key Words

ALTMEMPHY, DDR3, Design Example, External Memory, Multiple Controllers, Stratix IV, SIV 




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Version history
Last update:
‎06-27-2019 04:08 PM
Updated by: