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Design Example - SIV ALTMEMPHY RLDRAMII 400MHz x18 - Eight Controllers

Design Example - SIV ALTMEMPHY RLDRAMII 400MHz x18 - Eight Controllers



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Last Major Update

Initial Release - November 18th 2010 - SIVGX ALTMEMPHY RLDRAMII 400MHz, eight x18 interfaces, QuartusII v8.1

Design Overview

This design has 8 RLDRAM II controllers, 4 on the top and 4 on the bottom of the device. The PLL has been pulled out from inside the PHY to the top level of the Quartus II project. This design has one DLL and one PLL shared per 4 controllers. Since all 8 controllers have the same spec, this design uses one variation of the RLDRAM II reference design and instantiate it 8 times. This design is for fitting and timing closure purpose only, as in reality, the example driver for each controller will be different. Also, multiplexed address is used for this design. This design is not simulated or tested on a board. 

Design Specifications

Design files are located here. 

The table below lists the specifications for this design:  

AttributeSpecifcation
Quartus versionQuartusII v8.1
FPGAEP4SGX230KF40
KitNA
Memory deviceRLDRAMII
Memory speed400MHz
Memory topologyEight x18 devices
IP usedALTMEMPHY

 

Notes/Comments



Update History

  1. Initial Release - November 18th 2010 - SIVGX ALTMEMPHY RLDRAMII 400MHz, eight x18 interfaces, QuartusII v8.1

See Also

  1.   List of designs using Altera External Memory IP

 

External Links

  1. Altera's External Memory Interface Solutions Center
  2. Altera's External Memory Interface Handbook

 

Key Words

ALTMEMPHY, RLDRAMII, Design Example, External Memory, Stratix IV GX, SIV GX

 

 

  

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Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 04:12 PM
Updated by:
 
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