This design has 8 RLDRAM II controllers, 4 on the top and 4 on the bottom of the device. The PLL has been pulled out from inside the PHY to the top level of the Quartus II project. This design has one DLL and one PLL shared per 4 controllers. Since all 8 controllers have the same spec, this design uses one variation of the RLDRAM II reference design and instantiate it 8 times. This design is for fitting and timing closure purpose only, as in reality, the example driver for each controller will be different. Also, multiplexed address is used for this design. This design is not simulated or tested on a board.