Design Example - Soft Data Handler (Arria II)

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Design Example - Soft Data Handler (Arria II)

Design Example - Soft Data Handler (Arria II)


Design Specifications

The table below lists the specifications for this design:

Attribute Specification
Device Family Arria II GX
Quartus Version 13.0
Modelsim Version Modelsim SE v6.6d
Data rate 1.25Gbps
Data Pattern From Spirent Tester or User self generated
Number of Channel 1
IP used ALTGX GIGE, Transceiver Reconfiguration Controller

Design Objective

In transceiver GIGE mode, transceiver hard rate match FIFO is performing |I2|(BC50) character deletion/insertion during inter-packet gap and |C2|(BC42) character deletion/ insertion during Auto-Negotiation(AN) process. For further info on how transceiver rate match FIFO perform deletion/insertion in GIGE mode, please refer to Altera Device Handbook Vol.2, Transceiver Functional Modes chapter.


In certain user application, where Altera FPGA is used to a bridge between 2 devices and AN process was not happen at Altera FPGA device as shown in figure below.

b/bb/Senario1.jpg ( Senario1.jpg - click here to view image )


User might face the AN link failure between device A and B if have any deletion/insertion happen at Altera FPGA due to PPM difference. Accordingly to IEEE802.3,clause 36, Figure 36-7a-PCS receive state machine diagram,part a, received data at receiver side is consider correct if the data sequence is KDDD, where K= Control character, D= Data as shown in figure below.

c/c4/Receiver_state_machine.jpg ( Receiver state machine.jpg - click here to view image )


However, due to hard rate match FIFO limitation, only 2 byte data,KD (I2(BC50) / C2(BC42)) will be deleted/inserted only. Hence, the 2 byte data deletion/insertion will cause the AN process link failure.


In order to compensate the hard rate match FIFO limitation, Soft Data Handler is design in such the way that it will post-process receiver data and regenerate the correct data sequence of |C1| or |C2|, KDDD.(shown in figure below)

3/31/High_level.jpg ( High level.jpg - click here to view image )


Design Overview

Soft Data Handler Architecture Design

a/a8/Soft_data_handler_architecture_design.jpg ( Soft data handler architecture design.jpg - click here to view image )


Table 1 show the data pattern that will recognized by Soft Data Handler and the corresponding action.

Data Sequence Data Pattern from RX Action
1 KDDD Correct Data Sequence
2 KDKD Follow previous data
3 DDKD Swap KD
4 DDDD Replace DD with KD_C1 if the previous data is KDDD,KDKD,DDDD,DDKD,IIKD else pass through the data
5 IIII Correct sequence , pass through
6 KDII Pass through
7 IIKD Replace KD to II
8 DDII Replace DD with II if the previous data is KDDD,KDKD,DDKD,DDDD,IIKD else pass through the data
9 IIDD Pass through


Note: The reason to pass through is because maybe the data is error and Soft data handler will avoid correct the error.

  • The signal to trigger the start of Soft Data handler process is the rx_syncstatus from transceiver.
  • When rx_syncstatus signal is asserted, Word Aligner(WA) had align the correct word boundary.
  • The de-serializer block is used for group the 8-bit datain to 32-bit data. Serializer is convert the 32-bit data to 8-bit data.
  • The reason to group into 32-bit is because ease for data pattern detection.
  • The pattern detector block is used for isolate the whether the data is packet / AN data. This can be done by identify the “KD” as the start of process and when detect “I” as the stop of process.
  • Next, pattern detector will trigger Data converter block for conversion.
  • C1_C2 sequencer block will convert the data into C1 and C2 sequence.
  • Data converter block is used to convert the data to correct data sequence. The detail had been covered in the previous slides.


Design File Link

Soft Data Handler Design File (ZIP) 


External Link



AN 537: Implementing UNH-IOL Test Suite Compliance in Arria GX and Stratix II GX Gigabit Ethernet Designs (ver 1.0, Sep 2008, 514 KB) (PDF)


Key Words

Arria II, ALTGX GIGE , Soft Data Handler , Rate Match FIFO, Rate Matcher, GigE mode, IEEE 802.3 Clause 37 1000BASE-X Auto-Negotiation, SGMII Auto-Negotiation


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Version history
Last update:
‎12-14-2022 04:42 PM
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