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Design Example - Stratix II ALTMEMPHY DDR2 267MHz - Three Controllers

Design Example - Stratix II ALTMEMPHY DDR2 267MHz - Three Controllers

Last Major Update 

Initial Release - December 17th 2010 - SII ALTMEMPHY DDR2 267MHz, three interfaces (one interface is x72 and x8 for another two interfaces) , QuartusII v9.0 


Design Overview

This design has 3 controllers, 1 on the top and 2 on the bottom of the device. The DLL for the PHYs located at the bottom are instantiated externally and pulled out to the top level of the Quartus II project. The two bottom PHYs share one DLL. This design has two DLLs and three PLLs for 3 controllers. 

This design is for fitting and timing closure purpose only, as in reality, the example driver for each controller will be different. Although this design is timing closed with PCI Express Development Kit pinouts and simulated successfully, but this design was never tested on a board.

Design Specifications

Design files: StratixII_ALTMEMPHY_Multiple_DDR2_Controller.zip

The table below lists the specifications for this design:  

AttributeSpecification
Quartus versionQuartusII v9.0
FPGA 
EP2S90F1508C3
KitPCI Express Development Kit
Memory deviceQimonda HYS72T64000GU-3.7 for the x72 interface (top), JEDEC DDR2-533 512x8 generic device for the x8 interfaces (bottom)
Memory speed267MHz
Memory topologyComponent, x8 (Bottom Interface) , DIMM, x72 (Top Interface)
IP usedDDR2 High Performance Controller IP (ALTMEMPHY) and generated example top Quartus project


Notes/Comments

Update History

1. Initial Release - December 17th 2010 - SII ALTMEMPHY DDR2 SDRAM 267MHz, 2 x8 interfaces and 1 x72 interface, QuartusII v9.0


See Also

1. List of designs using Altera External Memory IP


External Links

1. Altera's External Memory Interface Solutions Center

2. Altera's External Memory Interface Handbook


Key Words

ALTMEMPHY, DDR2 SDRAM, Design Example, External Memory, Stratix II, SII

Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 04:53 PM
Updated by:
 
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