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Design Example - Stratix II DDR2 SDRAM ALTMEMPHY 200MHz x8 - Native Interface

Design Example - Stratix II DDR2 SDRAM ALTMEMPHY 200MHz x8 - Native Interface


Last Major Update

Initial Release – December 2010 - Stratix II, DDR2 SDRAM x8, 200MHz, Quartus II v9.1, Native interface with High Performance Controller II (HPC II) 


Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to successfully compile and simulate a DDR2 SDRAM interface working with a Stratix II FPGA using Native interface. The purpose of the lab is for the reader to get a basic feel for what steps are involved to use existing Native interface design with the High Performance Controller II (HPC II) architecture. The lab will not cover any of the steps in detail but simply show an overview of the design process.

The lab creates a 8-bit 200MHz DDR2 SDRAM external memory PHY and HPC II. The design contains a native-to-avalon adaptor module to enable designs with Native interface to work with the Avalon-MM interface of HPC II.

a/ae/Native_interface.JPG ( Native interface.JPG - click here to view image )


Design Specifications

The table below lists the specifications for this design: 

AttributeSpecification
Quartus versionQuartus II v9.1
FPGA deviceStratix II
Memory deviceDDR2 SDRAM
Memory speed200MHz
Memory topology8-bit
IP usedHigh Performance Controller II


Lab Steps

The lab uses Quartus II v9.1 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features.


A Quartus archive for this final project is included for reference.


Files for this lab are located in this zip file – native_to_avalon_adaptor.zip

 

Design Compilation

1. To compile the design example, perform the following steps:

   a. Launch the Quartus II software.

   b. On the File menu, click Open Project, navigate to <your project path>/native_to_avalon_adaptor_ref_de/native_to_avalon_adaptor_ref_de.qpf, and click Open.

   c. On the Processing menu, click Start Compilation.


Design Simulation

1. To set up the simulation environment, and start the simulation, perform the following steps:

   a. Launch ModelSim-Altera.

   b. On the File menu, click Change Directory.

   c. Select <your project path>/native_to_avalon_adaptor_ref_de/source/simulation/modelsim and click OK.

   d. On the Tools menu, click Tcl, then click Execute Macro. Select native_example_top_run_msim_rtl_verilog.tcl, and click Open to start the simulation.

 

Notes/Comments

This design example is not verified on hardware.

 

Update History

Initial Release – December 2010 - Stratix II, DDR2 SDRAM x8, 200MHz, Quartus II v9.1, Native interface with High Performance Controller II (HPC II) 

 

See Also 

1. List of designs using Altera External Memory IP 

 

External Links

1. Altera's External Memory Interface Solutions Center

2. Altera's External Memory Interface Handbook 

 

Key Words

High Performance Controller II (HPC II), DDR2, Design Example, External Memory, Stratix II, SII, Native interface



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‎06-27-2019 04:54 PM
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