Initial Release - December 15th 2010 – Stratix II GX DDR2 SDRAM x72 333MHz, Quartus II v7.2, DDR2 SDRAM High Performance Controller, Stratix II GX PCI Express development board.
This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a DDR2 SDRAM interface working with a Stratix II GX FPGA using DDR2 SDRAM on the Stratix II GX PCI Express development board. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the DDR2 High Performance Controller IP (ALTMEMPHY). The lab will not cover any of the steps in detail but simply show an overview of the design process. AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices should be used for a more thorough walkthrough.
The lab creates a 72bit 333MHz DDR2 SDRAM external memory PHY and controller using Altera’s DDR2 High Performance Controller IP (ALTMEMPHY). The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR2 SDRAM functionality
The table below lists the specifications for this design:
|Quartus version||QuartusII v7.2|
|Kit||Stratix II GX PCI Express development board|
|Memory device||Micron DDR2 SDRAM (4 MT47H32M16CC-3 and 1 MT47H64M8CB-3)|
|Memory topology||Four x16 components, and 1 x8 component with total x72|
|IP used||DDR2 High Performance Controller IP (ALTMEMPHY) and generated example top Quartus project|
A Quartus archive for the final project is also included for reference.
Files for this lab are located in this zip file – SII_DDR2_ALTMEMPHY.zip
Create a new folder for the project and place the files in it
1. Use the Megawizard Plug-in Manager to generate a DDR2 SDRAM high-performance controller
Start Quartus, open MegaWizard Plug-In Manager and create a new variation
2. Set parameters for Memory Controller with ALTMEMPHY
- Set Speed Grade to -3
- Set Memory Clock Frequency to 333.333MHz
- Set PLL Reference Clock Frequency to 100MHz
- Set Local interface clock frequency to Half
- For the Memory Presets, select JEDEC DDR2-667 256-Mb ×8, because preset for the MT47H32M16CC-3 or MT47H64M8CB-3 is not available
- Change the memory parameters to match with the specifications from the Micron MT47H32M16CC-3 and MT47H64M8CB-3 data sheet in the preset editor. Table below shows the memory parameter changes in Preset editor:
|Output clock pairs from FPGA||3|
|Total Memory interface DQ width||72|
|Maximum memory frequency for CAS|
|Maximum memory frequency for CAS|
|Memory on-die termination (ODT)||Disabled|
- Save this custom memory preset as Custom-PCI_SIIGX (JEDEC_DDR2-667_256Mb×8).
- Click OK to return to the Memory Settings panel.
- Under Address/Command Clock Settings, for Dedicated clock phase type 90.
- Under Board Timing Parameters, for Board skew type 20 ps.
- Under Auto-Calibration Simulation Options, select Quick Calibration
3. Set Top-Level Entity
The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their ALTMEMPHY IP configuration on hardware.
4. Add Timing Constraints
To add timing constraints, perform the following steps:
5. Assign the pin and DQ group settings
Run the tcl script <variation_name>__pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard
6. Assign the pin locations. Pin locations for external memory systems are not automatically created.
7. Add the Output Pin Load Assignments
Add the output pin load assignment for the various output and bi-directional pins on the Stratix II GX board as
8. Add the Termination or Current Strength Assignments
After executing the <variation_name>_pin_assignments.tcl file, use the Assignment Editor to make the following changes:
9. Do a Full Compile
Compile the example design.
1. Timing Analysis results
- Check the summary at the bottom of that report
- Check that all set up and hold timings pass
Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.
2. On board debug with Signal Tap
Open the Signal Tap file and reset the .sof file to the one just created with the full compilation
- The simulation will stop once the test complete signal goes high in the test bench
- Observe the results in the ModelSim Wave window
1. Initial Release - December 15th 2010 – SIIGX DDR2 x72 333MHz, QuartusII v7.2, DDR2 SDRAM High Performance Controller, Stratix II GX PCI Express development board
ALTMEMPHY, HPCI, DDR2, Design Example, External Memory, Stratix II GX, SII GX