Showing results for 
Search instead for 
Did you mean: 
836 Discussions

Design Example - Stratix II DDR2 SDRAM ALTMEMPHY 333MHz x72

Design Example - Stratix II DDR2 SDRAM ALTMEMPHY 333MHz x72

Last Major Update

Initial Release - December 15th 2010 – Stratix II GX DDR2 SDRAM x72 333MHz, Quartus II v7.2, DDR2 SDRAM High Performance Controller, Stratix II GX PCI Express development board.

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a DDR2 SDRAM interface working with a Stratix II GX FPGA using DDR2 SDRAM on the Stratix II GX PCI Express development board. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the DDR2 High Performance Controller IP (ALTMEMPHY). The lab will not cover any of the steps in detail but simply show an overview of the design process. AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices should be used for a more thorough walkthrough. 

The lab creates a 72bit 333MHz DDR2 SDRAM external memory PHY and controller using Altera’s DDR2 High Performance Controller IP (ALTMEMPHY). The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR2 SDRAM functionality

2/2f/StratixII_DDR2_ALTMEMPHY_Example.JPG ( StratixII DDR2 ALTMEMPHY Example.JPG - click here to view image )


Design Specifications

The table below lists the specifications for this design:  

Quartus versionQuartusII v7.2
KitStratix II GX PCI Express development board
Memory deviceMicron DDR2 SDRAM (4 MT47H32M16CC-3 and 1 MT47H64M8CB-3)
Memory speed333MHz
Memory topologyFour x16 components, and 1 x8 component with total x72
IP usedDDR2 High Performance Controller IP (ALTMEMPHY) and generated example top Quartus project



Lab Steps

A Quartus archive for the final project is also included for reference. 

Files for this lab are located in this zip file –

Create a new folder for the project and place the files in it


Design Generation

1. Use the Megawizard Plug-in Manager to generate a DDR2 SDRAM high-performance controller 

Start Quartus, open MegaWizard Plug-In Manager and create a new variation

  • In the Megawizard GUI, set device family to be Stratix II GX
  • The IP is located under the folders Interfaces/Memory Controller, choose DDR2 SDRAM Controller with ALTMEMPHY
  • Select Verilog HDL for the output file
  • For the name of the output file, browse to the folder you created above, give the instance the name “ddr2_Altmemphy”, click Open, click Next to open the IP GUI


2. Set parameters for Memory Controller with ALTMEMPHY 

  • Memory Settings Tab

   - Set Speed Grade to -3

    - Set Memory Clock Frequency to 333.333MHz 

    - Set PLL Reference Clock Frequency to 100MHz 

   - Set Local interface clock frequency to Half

  - For the Memory Presets, select JEDEC DDR2-667 256-Mb ×8, because preset for the MT47H32M16CC-3 or MT47H64M8CB-3 is not available

   - Change the memory parameters to match with the specifications from the Micron MT47H32M16CC-3 and MT47H64M8CB-3 data sheet in the preset editor. Table below shows the memory parameter changes in Preset editor:

Memory vendorMicron
Output clock pairs from FPGA3
Total Memory interface DQ width72
Maximum memory frequency for CAS
latency 3.0
200.000 MHz
Maximum memory frequency for CAS
latency 4.0
266.667 MHz
Memory on-die termination (ODT)Disabled
tREFI7.8 us


 - Save this custom memory preset as Custom-PCI_SIIGX (JEDEC_DDR2-667_256Mb×8).

 - Click OK to return to the Memory Settings panel.

  • PHY Settings Tab

  - Under Address/Command Clock Settings, for Dedicated clock phase type 90.

   - Under Board Timing Parameters, for Board skew type 20 ps.

   - Under Auto-Calibration Simulation Options, select Quick Calibration

  • Click Next
  • Click Next
  • Turn the Generate simulation model option
  • Click “Finish” to start IP generation. Check important messages during generation. After IP is successfully generated, click Exit to close GUI


3. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their ALTMEMPHY IP configuration on hardware.

  • Open the top-level entity file, <variation_name>_example_top.v or vhd
  • On the Project menu click Set as Top-Level Entity

4. Add Timing Constraints 

To add timing constraints, perform the following steps:

  • On the Assignments menu click Settings.
  • In the Category list, expand Timing Analysis Settings, and select TimeQuest
  • Timing Analyzer.
  • Select the <variation_name>_phy_ddr_timing.sdc file and click Add.
  • Click OK.

5. Assign the pin and DQ group settings 

Run the tcl script <variation_name>__pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard

  • Verify in the Assignment Editor that pin assignments have been created successfully

6. Assign the pin locations. Pin locations for external memory systems are not automatically created.

  • In the Quartus II software, on the Assignments menu, click Import Assignments...
  • When the Import Assignments dialog box appears, click the ... button to browse for the Altmemphy.qsf and select it.
  • Verify in Pin Planner or Assignment Editor that pin locations have been created successfully

7. Add the Output Pin Load Assignments 

Add the output pin load assignment for the various output and bi-directional pins on the Stratix II GX board as


  • Two of the CK and CK# clock pairs have two loads = 2 × 2 pF = 4 pF. The third CK/CK# clock output pair that drives the ×8 DDR2 SDRAM components has one load = 2 pF.
  • DQ and DQS pins (one load) = 4 pF
  • Addr/Cmd pins (five loads) = 5 × 2 pF = 10 pF

8. Add the Termination or Current Strength Assignments

After executing the <variation_name>_pin_assignments.tcl file, use the Assignment Editor to make the following changes:

  • Replace the SSTL-18 Class II I/O standard setting on all DQ and DQS pins (named mem_dq and mem_dqs) with the SSTL-18 Class I setting.
  • Delete the Termination setting of Series 50- or 25-Ohms without Calibration on all the DQ, DQS, DM, and CK/CK# pins (named mem_dq, mem_dqs, mem_dm, mem_clk, and mem_clk_n).
  •  Add a Current Strength assignment set to Maximum Current for all DQ, DQS, DM, and CK/CK# pins.

9. Do a Full Compile

Compile the example design.

Design Analysis

1. Timing Analysis results 

  • In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

- Check the summary at the bottom of that report 

- Check that all set up and hold timings pass 

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design. 

6/6a/StratixII_DDR2_ALTMEMPHY_Timing_Result.JPG ( StratixII DDR2 ALTMEMPHY Timing Result.JPG - click here to view image )

2. On board debug with Signal Tap 

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation 

  • Program the kit FPGA with the .sof
  • Run Signal Tap Analysis 
  • - Restart the driver 
  • - Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high. 
  • - Also check that calibration was successful and that the PLL is locked 


 Design Simulation

  • Run EDA RTL Simulation from Tools Menu – Run EDA Simulation Tool -> EDA RTL Simulation

- The simulation will stop once the test complete signal goes high in the test bench 

- Observe the results in the ModelSim Wave window 


Update History

 1. Initial Release - December 15th 2010 – SIIGX DDR2 x72 333MHz, QuartusII v7.2, DDR2 SDRAM High Performance Controller, Stratix II GX PCI Express development board


See Also

1. List of designs using Altera External Memory IP 

External Links

1. Altera's External Memory Interface Solutions Center 

2. AN328

Key Words

ALTMEMPHY, HPCI, DDR2, Design Example, External Memory, Stratix II GX, SII GX


Version history
Last update:
‎06-27-2019 04:54 PM
Updated by: