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Design Example - Stratix II GX DDR2 SDRAM LEGACY PHY 267MHz x72

Design Example - Stratix II GX DDR2 SDRAM LEGACY PHY 267MHz x72

Last Major Update 

Initial Release – December 2010 – Stratix II GX DDR2 SDRAM x72 267-MHz, QuartusII v7.2, Legacy PHY, Stratix II GX PCI Express (PIPE) Development Board.

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to create, constrain, and verify the operation of a 267-MHz/533-Mbps DDR2 SDRAM memory interface working on a Stratix II GX device using a Micron MT47H64M8CB-3 and four MT47H32M16CC-3 devices on the Stratix II GX PCI Express (PIPE) Development Board. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the DDR2 SDRAM Controller MegaCore (with the legacy-integrated static data path and controller). The lab will not cover any of the steps in detail but simply show an overview of the design process. Application Notes AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices should be used for a more thorough walkthrough.

The lab creates a 72 bit 267-MHz DDR2 SDRAM external memory PHY and controller using Altera’s DDR2 SDRAM High Performance Controller v7.2. The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 SDRAM functionality.

f/f7/Legacy_PHY.JPG ( Legacy PHY.JPG - click here view the image )

Design Specifications

The table below lists the specifications for this design:

Quartus versionQuartus II v 7.2
KitStratix II GX PCI Express (PIPE) Development Board
Memory deviceDDR2 SDRAM (a Micron MT47H64M8CB-3 and four MT47H32M16CC-3 devices)
Memory speed267MHz
Memory topologyx72-bit, 533-Mbps DDR2 SDRAM
IP usedDDR2 SDRAM Controller MegaCore and generated example top Quartus project


Lab Steps

The lab uses Quartus II v9.0 and MegaCore IP Library software version 9.0. The lab assumes the reader is a competent user of these tools and many of their features.


A Quartus archive for this final project is included for reference.

Files for this lab are located in this zip file –


Design Generation

1. Use the Megawizard Plug-in Manager to instantiate the PHY and a DDR2 SDRAM Controller MegaCore

Start Quartus, open MegaWizard Plug-In Manager and create a new variation

  • In the Megawizard GUI, set device family to be Stratix II GX
  • The IP is located under the folders Interfaces/Memory Controllers, choose DDR2 SDRAM Controller v9.0.
  • If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type
  • For the name of the output file, browse to the folder you created above, give the instance the name “legacy_core”, click click Next to open the IP GUI

2. Set parameters for DDR2 SDRAM Controller

Step 1: Parameterize 

a. Set MT47H64M16BT-37E as Preset

b. Set Clock Speed to 266.667 MHz.

c. Perform the following in Memory Tab:

  • Set Data bus width to 72
  • Set Number of clock pairs from FPGA to memory to 3
  • Set Bank address bits to 2

d. Perform the following in Controller Tab:

  • Enable the Use fedback clock
  • turn on the Insert extra pipeline registers in the datapath option

e. In the Controller Timings and Memory Timings pages, modify the numbers based on the MT47H32M16CC-3 or MT47H64M8CB-3 data sheet

f. Perform the following in Board Timing Tab

  • Turn on the Manual pin load control box.
  • Modify pin loading with the pin capacitance specification from the memory data sheet, as seen by the FPGA output pins
  • Modify the board timing information per the Stratix II GX PCI Express (PIPE) Development Board specification

g. In Project Settings Tab, turn off the Automatically verify datapath-specific timing in the Quartus II project option

h. In the Project Settings Tab, set Prefix all pins on the device with to mem_

i. Perform the following in Manual Timings Tab:

  • Turn on the Manual resynchronization control and Manual postamble control check boxes for the 2-PLL mode implementation
  • select dedicated clock in the Postamble clock setting pull-down list


Step 2: Constraints

Fix the location of the DQS and DQ pins per board specifications.

Step 3: Set Up Simulation

Turn on the Generate Simulation Model check box and choose either Verilog HDL or VHDL to generate a .vo (legacy_core.vo) file or a .vho (legacy_core.vho) file used to simulate the design.

Step 4: Generate

Click Generate to generate all the files needed for this memory interface. This action generates a summary of the interface when the generation is successful

3. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their ALTMEMPHY IP configuration on hardware. 

• Open the top-level entity file, Legacy_PHY.v

• On the Project menu click Set as Top-Level Entity

4. Add Timing Constraints

This step is required to constrain the design properly to have a reliable design running at the desired performance. Refer to AN 328 for a detail flow on adding the constraints to the design.

5. Do a Full Compile

This step is required prior to perform interface timing analysis. This should take about 10 minutes depending on the compiling PC.

6. Generate Timing Report

To analyze interface timing , run the dtw_timing_analysis.tcl script from the command prompt to analyze interface timing .

This script is available in the <quartus_installation_directory>\quartus\common\tcl\apps\gui\dtw folder.

3/36/Source_tcl_script.JPG ( Source tcl script.JPG - click here to view image )

After the dtw_timing_analysis.tcl script has finished running, close the compilation report and reopen it to display the script results. If the design does not meet timing, the design constraints must be adjusted. Refer to AN 328 for a detail flow on adjusting the constraints to the design.

Design Analysis

1. Timing Analysis results 

  • In the Compilation Report, Memory Interface Timing folder expand the legacy_core (ddr_setting.dwz)
  • - Check the summary at the bottom of that report

   - Check that all set up and hold timings pass

2. On board debug with Signal Tap 

To verify the functionality of the design example, download the design to the Stratix II GX PCI-Express Development Board. The design example contains a pnf

(pass not fail) signal that indicates whether the memory interface is functioning correctly.

To verify the interface signals, use the SignalTap Embedded Logic Analyzer for board testing.


Design Simulation
  • To run the simulation, perform the following steps:

   - Change the directory in the ModelSim Transcript window to <project_directory>/testbench/modelsim.

   - Set the memory model used for this simulation by entering the following:

      set memory_model ddr2

   - On the Tools menu, click Execute Macro and select




 For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

Update History

 Initial Release – December 2010 – SII GX DDR2 x72 267-MHz, QuartusII v7.2, Legacy PHY, Stratix II GX PCI Express (PIPE) Development Board.

See Also

1. List of designs using Altera External Memory IP 


External Links

1. Altera's External Memory Interface Solutions Center

2. Altera's External Memory Interface Handbook

3. AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices

4. DDR Timing Wizard (DTW) User Guide

Key Words

Legacy PHY, DD2 SDRAM, Design Example, External Memory , Stratix II GX, SII GX

Version history
Last update:
‎06-27-2019 04:55 PM
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