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Design Example - Stratix III ALTDQ DQS DDR2 SDRAM 333MHz x8

Design Example - Stratix III ALTDQ DQS DDR2 SDRAM 333MHz x8



Design Overview

This page describe how to implement an 8-bit wide, 150-MHz, 300-Mbps DDR2 SDRAM full-rate interface using the ALTDQ_DQS megafunction integrated with a few other megafunctions. The design targets the EP3SL150F1152C2 device, and an 8-bit wide 256-MB Micron MT47H32M8BP-3:B 333 MHz DDR2 SDRAM component.



Design Specifications

The design specifications are listed in the table below.

AttributeSpecification
Quartus II version11.0 
FPGA deviceEP3SL150F1152C2
External memory deviceDDR2 SDRAM (Micron MT47H32M8BP-3:B)
External memory speed333 MHz
IP usedALTDQ_DQS, ALTPLL, ALTDLL, ALTIOBUF

Figure 1 shows the example interface between the Stratix III EP3SL150F1152C2 device and an 8-bit wide 256-MB Micron MT47H32M8BP-3:B 333-MHz DDR2 SDRAM component. The CK, CK_N, CK_E, CS_N, RAS_N, CAS_N, WE_N, ODT, DM, BA[2:0], and ADDR[14:0] signals are output-only signals. DQ[7:0], DQS and DQS_N are bidirectional signals.

9/9a/Interface_StratixIII_with_DDR2_SDRAM.PNG ( Interface StratixIII with DDR2 SDRAM.PNG - click here to view image )



Design Generation

This section describes the steps required to instantiate a custom physical layer (PHY) implemented using Altera's megafunctions, as well as a custom designed controller. This design example is in Verilog HDL and consists of one top-level module or instance that connects 19 sub-modules or instances for a complete customized DDR2 interface with an SDRAM.

Create a Quartus II Project

Create a project in the Quartus II software that targets the EP3SL150F1152C2 device by performing the following steps.

  1. Open the altdll_altdq_dqs_DesignExample_ex1.zip file and extract the altdll_altdq_dqs_design_ex1.qar file.
  2. In the Quartus II software, restore the altdll_altdq_dqs_design_ex1.qar file into your working directory.
  3. Open the altdll_altdq_dqs_design_ex1.bdf file.

Generate the ALTPLL Megafunction

This design example uses the ALTPLL megafunction to implement two PLLs that clock the entire full-rate interface. Use the MegaWizard Plug-In Manager to instantiate two ALTPLL megafunctions with the following parameters:

pll_1:

  • in_clock = 50 MHz
  • mode = no compensation
  • c0 = 150 MHz, 0° phase shift. Used to clock the dll_1 instance. This PLL is dedicated to clock only the DLL.


pll_2:

  • in_clock = 50 MHz
  • mode = normal
  • c0 = 150 MHz, 0° phase shift. This is the mem_clk. It is used to clock the registers in the altdq_dqs_1 instance (the DQS output registers, the DQS OE registers, the DQS dynamic OCT registers, and DQ dynamic OCT registers), in the mem_clock_generate instance (the registers for generating CK and CK_N signals), the control_init_ddr instance (state machine for initialization of the DDR2), the control_write_ddr instance (state machine for writing data to the DDR2), the control_read_ddr instance (state machine for reading data from the DDR2), and the control_driver_ddr instance (state machine for driving the control_init_ddr instance, control_write_ddr instance, and control_read_ddr instance). It is also used to clock the registers in the addr_cmd_generate and addr_cmd_generate_oe instances which are used to generate the ADDR[14:0], BA[2:0], CK_E, CS_N, RAS_N, CAS_N, WE_N, and ODT signals.
  • c1 = 150 MHz, –90° phase shift. This is the write_clk. It is used to clock the registers in the altdq_dqs_1 instance (the DQ output registers and the DQ OE registers). 

Generate the ALTDLL Megafunction

This design example uses the ALTDLL megafunction to instantiate a DLL of the correct operational frequency (DQS signal frequency) of the custom external memory. This frequency setting depends on the bandwidth you want. Use the MegaWizard Plug-In Manager to instantiate a variations of the ALTDLL megafunction with the following parameters:

dll_1:

  • turn on jitter reduction = No
  • delay chain length = 12
  • delay buffer mode = low
  • DQS input frequency = 150 MHz
  • Instantiate DLL offset control A = No
  • Instantiate DLL offset control B = No
  • create ‘dll_aload’ port = No
  • create ‘dll_dqsupdate’ port = Yes

Generate the ALTDQ_DQS Megafunction

Next, you configure the settings for the dedicated circuitry for external memory interfaces using the ALTDQ_DQS megafunction. This custom DDR2 external memory interface consists of the following:

  • One pair of differential DQS/DQSn I/O pin (read or write strobe/clock)
  • Eight DQ I/O pins (read or write data)
  • One DM pin (output-only data mask)

The following section describes how to instantiate a variation of the ALTDQ_DQS megafunction with the correct parameter settings on each individual pages of the ALTDQ_DQS MegaWizard Plug-In Manager.


Page 3: Parameter Settings page

Page 3 of the ALTDQ_DQS MegaWizard Plug-In Manager is the Parameter Settings page. To configure the general settings for the ALTDQ_DQS instance, specify the options shown in the table below.

OptionValue
Number of bidirectional DQ8. There are 8 bidirectional DQ pins.
Number of input DQ0. Not used.
Number of output DQ1. There is 1 output only DM pin.
Number of stages in dqs_delay_chain3. This enables the DQS strobe signal to be centered with the DQ data (DQS signal must be +90° phase shifted)
DQS input frequencyEnter 150 MHz
Use half-rate componentsTurn off this option.
Use dynamic OCT pathTurn off this option.


Page 4: DQS IN Advanced Options page 

Page 4 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQS IN Advanced Options page. To configure the DQS input path of the ALTDQ_DQS instance, set the options shown in Table 2–2.

OptionValue
Enable DQS Input PathTurn on this option.
Delay chain usage:Select the Enable dqs_delay_chain option.
Advanced Delay Chain Options (DQS Delay Chain Phase Setting Options)Turn off the Select dynamically using configuration registers option.
Advanced Delay Chain Options (DQS Delay Chain Phase Setting Options)Select the DLL option.
Advanced Delay Chain Options (DQS Delay Buffer Mode)Select the Low option.
Advanced Delay Chain Options (DQS Phase Shift)Enter 9,000.
Advanced Delay Chain Options (Enable DQS offset control)Turn off this option.
Advanced Delay Chain Options (Enable DQS delay chain latches)Turn on this option.
Enable DQS busout delay chainTurn on this option.
Enable DQS enable blockTurn on this option.
Enable DQS enable control blockTurn on this option.
Advanced Enable Control Options (DQS Enable Control Phase Setting)Select the Set statically to ‘0’ option.
Advanced enable control options (DQS Enable Control Invert Phase)Select the Never option.
Enable DQS enable block delay chainTurn on this option.

 

Page 5: DQS OUT/OE Advanced Options page 

Page 5 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQS OUT/OE Advanced Options page. To configure the DQS OUTPUT and DQS OE path of the ALTDQ_DQS instance, select the options shown in Table 2–3.

OptionValue
Enable DQS output pathTurn on this option
DQS Output Path Options (Enable DQS output delay chain1)Turn on this option
DQS Output Path Options (Enable DQS output delay chain2)Select the DDIO option
DQS Output Path Options (DQS output register mode) Select the DDIO option
DQS Output Enable Options (Enable DQS output enable)Turn on this option
DQS Output Enable Options (Enable DQS output enable delay chain1)Turn on this option
DQS Output Enable Options (Enable DQS output enable delay chain2)Turn on this option
DQS Output Enable Options (DQS output enable register mode)Select the FF option

 

Page 6: DQ IN Advanced Options page

Page 6 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQ IN Advanced Options page. To configure the DQ input path of the ALTDQ_DQS instance, select the options shown in Table 2–4.

OptionValue
DQ Input Register Options (DQ input register mode)Select DDIO option.
DQ Input Register Options (DQ input register clock source)Select the ‘dqs_bus_out’ port option and disable the
‘Connect DDIO clkn to DQS_BUS from complementary DQSn’ option.
DQ Input Register Options (Use DQ input phase alignment)Turn on this option
Advanced DQ IPA options:(DQ Input Phase Alignment Phase Setting)

Select the Set statically to ‘0’ option.

Advanced DQ IPA options: (Add DQ Input Phase Alignment Input Cycle Delay)Select the Never option.
Advanced DQ IPA options: (Invert DQ Input Phase Alignment Phase)Select the Never option.
Advanced DQ IPA options: (Register DQ input phase alignment bypass output)Turn on this option
Advanced DQ IPA options: (Register DQ input phase alignment add phase transfer)Turn on this option
DQ Input Register Options (Use DQ half rate ‘dataoutbypass’ port)Turn on this option
Use DQ input delay chainTurn on this option


Page 7: DQ OUT/OE Advanced Options page

Page 7 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQ OUT/OE Advanced Options page. To configure the DQ OUTPUT and DQ OE path of the ALTDQ_DQS instance, select the options shown in Table 2–5.

OptionValue
DQ Output Path Options (Enable DQ output delay chain1)Turn on this option
DQ Output Path Options (Enable DQ output delay chain2)Turn on this option
DQ Output Path Options (DQ output register mode)Select the DDIO option
DQ Output Enable Options (Enable DQ output enable)Turn on this option
DQ Output Enable Options (Enable DQ output enable delay chain1)Turn on this option
DQ Output Enable Options (Enable DQ output enable delay chain2)Turn on this option
DQ Output Enable Options (DQ output enable register mode)Select the FF option


Page 8: Half-rate Advanced Options page

Page 8 of the ALTDQ_DQS MegaWizard Plug-In Manager is the Half-rate Advanced Options page. To configure the half-rate settings of the ALTDQ_DQS instance, select the options shown in Table 2–6.

OptionValue
IO Clock Divider SourceTurn off this option. This option is not applicable for full-rate interface.
Create ‘io_clock_divider_masterin’ input portTurn off this option. This option is not applicable for full-rate interface.
Create ‘io_clock_divider_clkout’ output portTurn off this option. This option is not applicable for full-rate interface.
Create ‘io_clock_divider_slaveout’ output portTurn off this option. This option is not applicable for full-rate interface.
IO Clock Divider Invert PhaseSelect the Never option. Not applicable for fullrate interface



Page 9: OCT Path Advanced Options page

Page 9 of the ALTDQ_DQS MegaWizard Plug-In Manager is the OCT Path Advanced Options page. To configure the OCT registers and delay chain settings of the ALTDQ_DQS instance, select the options shown in Table 2–7.

OptionValue
Dynamic OCT Options (Enable OCT delay chain 1)Turn off this option. This option is not applicable for full-rate interface.
Dynamic OCT Options (Enable OCT delay chain 2)Turn off this option. This option is not applicable for full-rate interface.
DQ Output Path Options (OCT register mode)Turn off this option. This option is not applicable for full-rate interface.


Page 10: DQS/DQSn IO Advanced Options page

Page 10 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQS/DQSn IO Advanced Options page. Select options shown in Table 2–8.

OptionValue
Use DQSn I/OTurn on this option.
DQS and DQSn IO Configuration modeSelect the Differential Pair option. This is required for this particular scenario.


Page 11: Reset Ports Advanced Options page

Page 11 of the ALTDQ_DQS MegaWizard Plug-In Manager is the Reset Ports Advanced Options page. Select options shown in Table 2–9.

OptionValue
Create ‘dqs_areset’ input portTurn on this option
Create ‘dqs_sreset’ input portTurn off this option
Create ‘input_dq_areset’ input portTurn off this option
Create ‘input_dq_sreset’ input portTurn off this option
Create ‘output_dq_areset’ input portTurn on this option
Create ‘output_dq_sreset’ input portTurn off this option
Create ‘bidir_dq_areset’ input portTurn on this option
Create ‘bidir_dq_sreset’ input portTurn off this option


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Last update:
‎06-27-2019 04:20 PM
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