Community
cancel
Showing results for 
Search instead for 
Did you mean: 

Design Example - Stratix III ALTDQ DQS DDR2 SDRAM 333MHz x8


Generate the ALTIOBUF Megafunction

For an external memory interface, the DQ, DQS, DQSn, DM, ADDR[14:0], BA[2:0], CK, CK_N, CK_E, CS_N, RAS_N, CAS_N, WE_N, and ODT pins must be connected to I/O buffers via the ALTIOBUF megafunction. There are 14 interface signals for this design example that need I/O buffers to be interfaced with the FPGA pins. These I/O buffers are contained in the dqs_io_buffer, ck_io_buffer, dq_io_buffer, dm_io_buffer, addr_io_buffer, ba_io_buffer, and cmd_io_buffer instances. There are 35 I/O buffers used in this instance. Table 2–10 shows the requirements that must be set for these signals in the I/O buffer instances.

SignalInstanceRequirement
DQS and DQS_N dqs_io_buffer1-bit bidirectional I/O buffer with differential capabilities enabled
CK and CK_Nck_io_buffer2-bit output I/O buffer with differential capabilities enabled
DQ[7:0]dq_io_buffer8-bit bidirectional I/O bufferI/O buffer
DMdm_io_buffer1-bit output I/O buffer
ADDR[14:0]addr_io_buffer15-bit output I/O buffer
BA[2:0]ba_io_buffer3-bit output I/O buffer
CK_Ecmd_io_buffer1-bit output I/O buffer
CS_Ncmd_io_buffer1-bit output I/O buffer
RAS_Ncmd_io_buffer1-bit output I/O buffer
CAS_Ncmd_io_buffer1-bit output I/O buffer
WE_Ncmd_io_buffer1-bit output I/O buffer
ODTcmd_io_buffer1-bit output I/O buffer

Design Customized Memory Controller Datapath Logic

Because this is a custom external memory interface for DDR2 interface, you must design the necessary datapath to control the CK, CK_N, ADDR[14:0], BA[2:0], CK_E, CS_N, RAS_N, CAS_N, WE_N, and ODT signals. Altera provides a design example that you can use to create your own logic. In the Altera-provided design example, the datapath of the CK and CK_N signals are controlled by the mem_clock_generate instance. This instance consists of two DDIO_OUT blocks. For the CK signal, the inputs of the DDIO_OUT block are each tied to VCC and GND. For the CK_N signal, the inputs of the DDIO_OUT block are each tied to GND and VCC to reflect the inverse of the CK signal. The addr_cmd_generate instance controls the datapath of the ADDR[14:0], BA[2:0], CK_E, CS_N, RAS_N, CAS_N, WE_N, and ODT signals. This ddr_cmd_generate instance consists of 24 DDIO_OUT blocks to individually represent the 24 signals. For these signals, there are 24 DFF blocks to control their respective OE (output enable) signals. The OE signals are controlled by the addr_cmd_generate_oe instance. The inputs of these 48 blocks are fed accordingly with data, depending on the three state machines that act as the control path of the customized memory controller. The three state machines are as follows:

  • control_init_ddr instance
  • control_write_ddr instance
  • control_driver_ddr instance

Multiplexer Instances

There are two multiplexer instances: cmd_addr_mux_1 and dqs_dqsn_dq_dm_mux_1.

cmd_addr_mux_1

The cmd_addr_mux_1 instance is a 144-bit to 72-bit multiplexer with a 1-bit select signal. The cmd_addr_mux_1 instance multiplexes the CK_E, CK_N, RAS_N, CAS_N, WE_N, BA_OE, BA_DATA, ADDR_OE, ADDR_DATA and ODT signals from the following two control path state machines of the customized memory controller: 

  • control_init_ddr instance
  • control_write_ddr instance

The output of the multiplexer is sent to the data path of the command and address instances, addr_cmd_generate and addr_cmd_generate_oe. For this multiplexer, the control_driver_ddr instance controls the 1-bit select.

dqs_dqsn_dq_dmr_mux_1

The dqs_dqsn_dq_dmr_mux_1 instance is a 66-bit to 33-bit multiplexer with a 1-bit select signal. The dqs_dqsn_dq_dmr_mux_1 instance multiplexes the dm_oe, dm_data, dq_oe, dq_data, dqs_oe, dqs_data, dqsn_oe, and dqsn_data signals from the following two control path state machines of the customized memory controller:

  • control_init_ddr instance
  • control_write_ddr instance

The output of the multiplexer is sent to the data path of the DQS, DQSN, DQ, and DM (ALTDQ_DQS instance), which is the altdq_dqs_1 instance. The 1-bit select for this multiplexer is controlled by the control_driver_ddr instance. This completes the steps for the customized memory controller datapath logic to generate the CK,CK_N, ADDR[14:0], BA[2:0], CK_E, CS_N, RAS_N, CAS_N, WE_N, and ODT signals.

Design Customized Memory Controller Control Path Logic

Because this is a custom external memory interface for the DDR and DDR2 interface, you must design control path logic to control the DQS, DQS_N, DQ, DM, A (address), BA (bank address), CK, CK#, CKE, CS#, RAS#, CAS#, WE#, and ODT signals from the FPGA core. The design example contains three state machines to control these signals to enable proper operation of the external memory interface. These state machines are as follows:

  • control_init_ddr instance

The control_init_ddr instance initializes the DDR2 component for the proper interface operation following the timing requirements as specified in the specific Micron DDR2 datasheet. Because the ALTMEMPHY megafunction does not support a burst length of 8, the customized memory controller in this design example initialized the DDR2 for this mode of operation.

  • control_write_ddr instance

The control_write_ddr instance writes a set of 8 data to the memory array in the DDR2 component following the timing requirements as specified in the specific Micron DDR2 datasheet.

  • control_driver_ddr instance

The control_driver_ddr instance coordinates the two state machines (control_init_ddr and control_write_ddr instances) following the timing requirements as specified in the specific Micron DDR2 datasheet to enable proper operation of this design example. This includes sequentially enabling the following instances:

  • The control_init_ddr instance state machine to initialize the DDR2 component
  • The control_write_ddr instance state machine to write the data to the memory array in the DDR2 component

The state machine also controls the select signals of the two multiplexers (cmd_addr_mux_1 and dqs_dqsn_dq_dm_mux_1) depending on which of the two control path state machine is currently active.

Add Constraints

After instantiating the necessary instances to create a customized DDR2 memory controller from the “Instantiate PHY (via ALTDLL and ALTDQ_DQS) and (Custom-Designed) Controller in a Quartus II Project” stage, you must generate the constraints files for the design example. Apply these constraints to the design before compilation. You must manually specify constraints because this design example does not use the ALTMEMPHY megafunction or the DDR2 SDRAM high-performance controller.

Add Timing Constraints

When you instantiate the customized DDR2 memory controller design, it does not automatically generate a timing constraint file (SDC file). You must manually create your own SDC file to constrain the timing on this design. This design example comes with a timing constraints file, top_custom_ddr2_controller_phy_ddr_timing.sdc. The timing constraint file constrains the clocks on the customized DDR2 memory controller design. To add timing constraints, perform the following steps:

  1. On the Assignments menu, click Settings.
  2. In the Category list, expand Timing Analysis Settings and select TimeQuest Timing Analyzer.
  3. Select the top_custom_ddr2_controller_phy_ddr_timing.sdc file and click Add.
  4. Click OK.

Set Optimization Technique

To ensure the remaining unconstrained paths are routed with the highest speed and efficiency, set the optimization technique to Speed. To set the optimization technique, perform the following steps:

  1. On the Assignments menu, click Settings.
  2. Select Analysis & Synthesis Settings.
  3. Under Optimization Technique, select Speed.
  4. Click OK.

Set Fitter Effort

To set the Fitter effort to Standard Fit, perform the following steps:

  1. On the Assignments menu, click Settings.
  2. Expand Fitter Settings.
  3. Turn on Optimize Hold Timing and select All Paths.
  4. Turn on Optimize Fast Corner Timing.
  5. Under Fitter Effort, select Standard Fit.
  6. Click OK.

Enter Pin Location Assignments

To enter the pin location assignments, perform the following steps:

  1. On the Processing menu, point to Start, and click Start Analysis and Synthesis.
  2. Assign all your pins, so the Quartus II software fits your design correctly and gives correct timing analysis. To assign pin locations for the Stratix III development kit, run the top_custom_ddr2_controller_PinLocations.tcl file, which is provided with the design example or manually assign pin locations with the Pin Planner using the Stratix III FPGA Development Kit at the Altera website.

<note> If you are at the design exploration phase of your design cycle and do not have any PCB defined pin locations, you should still manually define an initial set of pin constraints, which can become more specific during your development process.

To manually assign pin locations, perform the following steps:

  1. Open Pin Planner. On the Assignments menu, click Pin Planner.
  2. Assign DQ and DQS pins.

a. To select the device DQS pin groups that the design uses, assign each DQS pin in your design to the required DQS pin in the Pin Planner. The Quartus II Fitter then automatically places the respective DQ signals onto suitable DQ pins within each group. To see the DQS groups in Pin Planner, right click, select Show DQ/DQS Pins, and click In ×8/×9 Mode. Pin Planner shows each DQS group in a different color and with a different legend: S = DQS pin, Sbar = DQSn pin, and Q = DQ pin.

<note> Most DDR2 SDRAM devices operate in ×8/×9 mode. However, some DDR2 SDRAM devices operate in ×4 mode. Refer to your specific memory device datasheet.

b. Select the DQ mode to match the DQ group width (number of DQ pins/number of DQS pins) of your memory device. DQ mode is not related to the memory interface width.

<note> The DQ group order and DQ pin order in each group is not important. However, you must place DQ pins in the same group as their respective strobe pin.

  1. Place DM pins in their respective DQ group.
  2. Place address and control command pins on any spare I/O pins ideally in the same bank or side of the device as the CK and CK_N pins.
  3. Ensure you place CK and CK_N pins on differential I/O pairs for the CK/CK# pin pair. To identify differential I/O pairs, right-click in Pin Planner and select Show Differential Pin Pair Connections. Pin pairs show a red line between each pin pair.

        <note> You must place CK and CK_N on a DIFFIO_RX pin pair, if your design uses differential DQS signaling.

  1. Place the clock_source pin on a dedicated PLL clock input pin with a direct connection to this design example's PLL and DLL pair—usually on the same side of the device as your memory interface. This recommendation reduces PLL jitter, saves a global clock resource, and eases timing and fitter effort.
  2. Place the global_reset pin (like any high fan-out signal) on a dedicated clock pin.

Board Trace Delay Models

For accurate I/O timing analysis, you must specify the board trace and loading information. This information should be derived and refined during your PCB development process of pre-layout (line) simulation and finally post-layout (board) simulation.

Compile Design and Verify Timing

Before compiling the design, set the top-level entity of the project. The design example top-level file is top_custom_ddr2_controller.v, which connects 13 other sub-modules or instances for a complete customized memory controller for DDR2.

To set the top-level file, perform the following steps:

  1. Open the top-level entity file, top_custom_ddr2_controller.v.
  2. On the Project menu, click Set as Top-Level Entity.

To compile the design, on the Processing menu, click Start Compilation. After successfully compiling the design, run the TimeQuest timing analyzer to verify the timing based on the SDC file. If the timing margin report shows negative hold time on the address and command datapath, adjusting the clock that is regulating the address and command output registers can improve the hold margin on the address and command datapath.

Perform Functional Simulation  

After you have compiled your design, set up and simulate the design in the ModelSim-Altera software by performing the following steps:

  1. Unzip the top_custom_ddr2_controller_msim.zip file to any directory on your PC. Obtain and copy the vendors memory Verilog HDL simulation model to the directory where the previous zip file was uncompressed. This can be retrieved from the Micron website. Get the ddr2.v, ddr2_mcp.v, and ddr2_parameters.vh memory model files from the Micron website and save them in the directory of this design example.
  2. Open the memory model file (ddr2.v) in a text editor and add the following define statements to the top of the file:

'define sg3

'define ×8

'define MAX_MEM

The three define statements prepare the DDR2 SDRAM interface model.

The first statement specifies the memory device speed grade as –3.

The second statement specifies the memory device width per DQS.

The third statement says to allocate memory for every address supported by the DDR2 model.

  1. Open the testbench (tb_top_custom_ddr2_controller.v) from the directory in a text editor, instantiate the downloaded memory model, and connect its signals to the rest of the design.
  2. Start the ModelSim® software.
  3. On the File menu, click Change Directory.
  4. Select the folder in which you unzipped the files.
  5. On the Tools menu, click Execute Macro.
  6. Select the top_custom_ddr2_controller_msim.do file and click Open. This is a script file for the ModelSim-Altera software to automate the necessary settings for the simulation.
  7. Verify the results shown in the Wave window.

Files

Original copy of EMI HB Volume 5 Chapter 1: Implementing Custom Memory Interface PHY

Design Example Files

Revision History

Initial Release: July 2011.

See Also

  1. List of designs using Altera External Memory IP

External Links

  1. Altera's External Memory Interface Solutions Center 
  2. Altera's External Memory Interface Handbook

Key Words

ALTDQ_DQS, DDR2, SDRAM, Design Example, External Memory, EMI, Stratix III, SIII

Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 04:21 PM
Updated by:
 
Contributors