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Design Example - Stratix III DDR2 SDRAM ALTMEMPHY x72 UDIMM 400MHz

Design Example - Stratix III DDR2 SDRAM ALTMEMPHY x72 UDIMM 400MHz

Last Major Update

Initial Release - December 13th 2010 – Stratix III DDR2 SDRAM x72 400MHz, Quartus II v9.0, DDR2 SDRAM High Performance Controller, Stratix III FPGA development kit. 

 Design Overview

 This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a DDR2 SDRAM interface working with a Stratix III FPGA using DDR2 SDRAM UDIMM on the Stratix III FPGA development kit. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the DDR2 High Performance Controller IP (ALTMEMPHY). The lab will not cover any of the steps in detail but simply show an overview of the design process. Volume 6 of the External Memory Interface Handbook should be used for a more thorough walkthrough. 

The lab creates a 72bit 400MHz DDR2 SDRAM external memory PHY and controller using Altera’s DDR2 High Performance Controller IP (ALTMEMPHY). The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR2 SDRAM functionality

Design Specifications

The table below lists the specifications for this design:  

Quartus versionQuartusII v9.0
KitStratix III FPGA development kit
Memory deviceDDR2 SDRAM (Micron MT9HTF12872AY-800)
Memory speed400MHz
Memory topologyUnbuffered DIMM, x72
IP usedDDR2 High Performance Controller IP (ALTMEMPHY) and generated example top Quartus project


Lab Steps

The lab uses Quartus II v9.0 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

Four files have been pre-designed for this lab to save time. 

  • A pin location assignments tcl script
  • A signal tap file for debug of the interface design that has been created
  • A board trace models for Stratix III FPGA development kit tcl script
  • An example driver “output ports” virtual pin assignments script

A Quartus archive for the final project is also included for reference. 

Files for this lab are located in this zip file –

Create a new folder for the project and place the files in it

 Design Generation

1. Use the Megawizard Plug-in Manager to generate a DDR2 SDRAM high-performance controller

  • Start Quartus, open MegaWizard Plug-In Manager and create a new variation
  • In the Megawizard GUI, set device family to be Stratix III
  • The IP is located under the folders Interfaces/External Memory/DDR2 SDRAM, choose DDR2 SDRAM Controller with ALTMEMPHY
  • If your license for ModelSim can not support multiple HDL languages then chose verilog as output file type
  • For the name of the output file, browse to the folder you created above, give the instance the name “ddr2_dimm”, click Open, click Next to open the IP GUI


2. Set parameters for Memory Controller with ALTMEMPHY 

  • Memory Settings Tab 

    - Set Speed Grade to 2

    - Set Memory Clock Frequency to 400MHz 

     - Set PLL Reference Clock Frequency to 50MHz 

    - For the Memory Presets, select Micron MT9HTF12872AY-800, which gives a 72-bit wide 1-GB 400-MHz DDR2 DIMM

    - Change tIS, tIH, tDS, and tDH parameters in the Memory Preset with the derated parameters after running board simulation 

           i) Address and command = 0.5 V/ns

           ii) CLK and CLK# = 1.5 V/ns (differential)

           iii) DQ = 1.5 V/ns

           iv) DQS and DQSn = 2.8 V/ns (differential)

         Hence, the correct tIS, tIH, tDS, and tDH values for this design are:

                ■ tIS = tISb + tIS + (VIHAC – VREF)/address and command rising slew rate

                      = 175 +(– 30) +400 = 545 ps

                 ■ tIH = tIHb + tIH + (VREF – VILDC)/address and command rising slew rate

                         = 250 +(– 95) +250 = 405 ps

                 ■ tDS = tDSa + tDS + (VIHAC – VREF)/DQ rising slew rate

                          = 50 + 67 +133 = 250ps

                ■ tDH = tDHa + tDH + (VREF – VILDC)/DQ rising slew rate

                          = 125 + 42 +83 = 250 ps

  • PHY Settings Tab

      - Turn on Use differential DQS under Advanced PHY

      - Turn on the Enable dynamic parallel on-chip termination (OCT) option

     - Under Address/Command Clock Settings, for Dedicated clock phase type 240. 

      - Under Board Timing Parameters, for Board skew type 20 ps.

  • Click Next
  • Click Next
  • Turn the Generate simulation model option
  • Click “Finish” to start IP generation. Check important messages during generation.


3. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their ALTMEMPHY IP configuration on hardware.

  • Open the top-level entity file, <variation_name>_example_top.v or vhd
  • On the Project menu click Set as Top-Level Entity


4. Add Timing Constraints 

To add timing constraints, perform the following steps:

  • On the Assignments menu click Settings.
  • In the Category list, expand Timing Analysis Settings, and select TimeQuest Timing Analyzer.
  • Select the <variation_name>_phy_ddr_timing.sdc file and click Add.
  • Click OK.


5. Assign the pin and DQ group settings 

Run the tcl script <variation_name>__pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard

  • Verify in the Assignment Editor that pin assignments have been created successfully


6. Assign the pin locations. Pin locations for external memory systems are not automatically created.

  •  Run the S3_Host_DDR2_PinLocations.tcl script to assign pin locations for the targeted kit
  •  Run the s3_host_ddr2_exdriver_vpin.tcl script to assign example driver "output ports" virtual pin
  •  Verify in Pin Planner or Assignment Editor that pin locations have been created successfully


7. Enter board trace models

  •  Run the S3_Host_DDR2_BTModels.tcl script to enter the board trace model for the targeted kit 

8. Advanced I/O Timing

ALTMEMPHY-based designs assume that the memory address and command signals are matched length to the memory clock signals. Typically, this length match is not true for DIMM-based designs. You should verify the difference in your design. For the Stratix III development board fitted with the MT9HTF12872AY DIMM, the address and command signals remain asserted 750 ps longer than the clock signals.

  • Open the ddr2_dimm_phy_ddr_timing.sdc file in a text editor and find the following line (usually line 31):

set t(additional_addresscmd_tpd) 0.000

  • Change the line to the following text:

set t(additional_addresscmd_tpd) 0.750

  • Save the file


9. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.

Design Analysis

1. Timing Analysis results

In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

  • Check the summary at the bottom of that report
  • Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design. 

0/05/StratixIII_DDR2_ALTMEMPHY_TimingAnalysis_Result.JPG ( StratixIII DDR2 ALTMEMPHY TimingAnalysis Result.JPG - click here to view image )

2. On board debug with Signal Tap 

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation

  • Program the kit FPGA with the .sof
  • Run Signal Tap Analysis

      - Restart the driver

       - Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high. 

      - Also check that pnf and pnf_per_byte is high. 

2/2a/StratixIII_DDR2_SDRAM_ALTMEMPHY_SignalTap_Result.JPG ( StratixIII DDR2 SDRAM ALTMEMPHY SignalTap Result.JPG - click here to view image )

 Design Simulation

  • Run EDA RTL Simulation from Tools Menu – Run EDA Simulation Tool -> EDA RTL Simulation

    - The simulation will stop once the test complete signal goes high in the test bench

     - Observe the results in the ModelSim Wave window 



 Update History

1. Initial Release - December 13th 2010 - SIII DDR2 x72 400MHz, QuartusII v9.0, DDR2 SDRAM High Performance Controller, Stratix III FPGA development kit.

See Also

1. List of designs using Altera External Memory IP 

 External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

Key Words

ALTMEMPHY, HPCI, DDR2, Design Example, External Memory, Stratix III, SIII


Version history
Last update:
‎06-27-2019 04:22 PM
Updated by: