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Design Example - Stratix III DDR2 SDRAM SODIMM ALTMEMPHY 333MHz x64

Design Example - Stratix III DDR2 SDRAM SODIMM ALTMEMPHY 333MHz x64

Last Major Update

Initial Release – December 2010 – Stratix III DDR2 SDRAM SODIMM x64 333MHz, Quartus II v8.0SP1, DDR2 SDRAM High Performance Controller with ALTMEMPHY.

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to design a 64-bit wide, 333-MHz, 667-Mbps DDR2 SDRAM interface working with a Stratix III FPGA using four Micron MT16HTF25664HY discrete components . The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the ALTMEMPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process.

The ALTMEMPHY IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 SDRAM functionality 

Design Specifications

The table below lists the specifications for this design:

Quartus versionQuartusII v8.0SP1
Memory deviceDDR2 SDRAM (Micron MT16HTF25664HY)
Memory speed333MHz
Memory topologyFour x16-bit,667-Mbps DDR2 discrete devices
IP usedDDR2 SDRAM High Performance Controller with ALTMEMPHY IP and generated example top Quartus project

Lab Steps

The lab uses Quartus II v8.0 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

A signal tap file has been created for debug of the interface design for this lab to save time.

A Quartus archive for the final project is also included for reference. 

Files for this lab are located in this zip file – .

Create a new folder for the project and place the files in it.

Design Generation

1. Use the Megawizard Plug-in Manager to generate a DDR3 SDRAM High Performance Controller 

Copy the memory parameters files, ddr2a.xml, to your <installation directory>\80sp1\ip\ddr3_high_perf\lib directory.

Start Quartus, open MegaWizard Plug-In Manager and create a new variation

  • In the Megawizard GUI, set device family to be Stratix III

  • The IP is located under the folders Interfaces/Memory Controllers, choose DDR2 SDRAM High Performance Controller v8.0

  • If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type

  • For the name of the output file, browse to the folder you created above, give the instance the name “ddr2_dimm”, click Open, click Next to open the IP GUI


2. Set parameters for Memory Controller with ALTMEMPHY

  • General Settings Tab

   - Set Speed grade to 3.

   - Set PLL reference clock frequency to 25 MHz.

   - Set Memory clock frequency to 333.333 MHz

  • PHY Settings Tab

   - Turn on Enable dynamic parallel on-chip termination (OCT) option under Advanced PHY

   - Under Address/Command Clock Settings, for Dedicated clock phase type 240.

   - Under Board Timing Parameters, for Board skew type 35 ps.

  • Controller Interface Settings Tab

   - Keep all default settings

   - Click Next

  • Turn on the Generate simulation model option
  • Click “Finish” to start IP generation. Check important messages during generation. After IP is successfully generated, click Exit to close GUI  

3. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their ALTMEMPHY IP configuration on hardware.

  • Open the top-level entity file, <variation_name>_example_top.v or vhd
  • On the Project menu click Set as Top-Level Entity

4. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the ALTMEMPHY for when the I/O assignments are created in the next step.

5. Set Optimization Technique

This step is required to ensure the remaining unconstrained paths are routed with the highest speed and efficiency. To set the optimization technique, perform the following steps:

  • On the Assignments menu, click Settings.
  • Select Analysis & Synthesis Settings
  • Select Speed under Optimization Technique. Click OK.

6. Set Fitter Effort

To set the fitter effort, perform the following steps:

  • On the Assignments menu, click Settings
  • Select Fitter Settings
  • Turn on Optimize hold timing and select All Paths
  • Turn on Optimize multi-corner timing
  • Select Standard Fit (highest effort) under Fitter effort
  • Click OK.


7. Add Timing Constraints 

To add timing constraints, perform the following steps:

  • On the Assignments menu click Settings
  • In the Category list, expand Timing Analysis Settings, and select TimeQuest
  • Timing Analyzer
  • Select the <variation_name>_phy_ddr_timing.sdc file and click Add
  • Click OK

8. Assign the pin and DQ group settings 

Run the tcl script ddr2a_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard

  • Verify in the Assignment Editor that pin assignments have been created successfully

9. Assign the pin locations 

Pin locations for external memory systems are not automatically created. You need to manually assign these pin locations and verify in Pin Planner or Assignment Editor that pin locations have been created successfully.

10. Assign I/O Standards

To assign the I/O standards, perform the following steps:

  • On the Assignments menu, click Assignment Editor.
  • Specify 3.3-V LVTTL as the I/O standard for clock_source.

11. Assign Virtual Pins

To assign virtual pins, perform the following steps:

  • On the Assignments menu, click Assignment Editor
  • Specify Virtual Pin as the I/O standard for test_complete, pnf, pnf_per_byte, and test_sig

12. Enter board trace models 

To enter board trace information for accurate I/O timing analysis, perform the following steps:

  • In Pin Planner, select the pin or group of pins that you want to enter the information for
  • Right-click and select Board Trace Model

13. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.

Design Analysis

1. Timing Analysis results

  • In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

   - Check the summary at the bottom of that report

   - Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.


2. On board debug with Signal Tap 

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation

  • Program the kit FPGA with the .sof
  • Run Signal Tap Analysis

   - Restart the driver

   - Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.

   - Also check that calibration was successful and that the PLL is locked

Design Simulation
  • Run EDA RTL Simulation from Tools Menu – Run EDA Simulation Tool -> EDA RTL Simulation

   - The simulation will stop once the test complete signal goes high in the test bench

   - CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset

   - Observe the results in the ModelSim Wave window


For a list of supported and unsupported features in the DDR2 SDRAM Controller with ALTMEMPHY, refer to the DDR and DDR2 SDRAM Controller with ALTMEMPHY IP User Guide. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

Update History

Initial Release – December 2010 – Stratix III DDR2 SDRAM SODIMM x64 333MHz, Quartus II v8.0SP1, DDR2 SDRAM High Performance Controller with ALTMEMPHY.

See Also

1. List of designs using Altera External Memory IP 

External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

Key Words

ALTMEMPHY, DDR2 SDRAM SODIMM, Design Example, External Memory, Stratix III, SIII

Version history
Last update:
‎06-27-2019 04:22 PM
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