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Design Example - Stratix III DDR2 SDRAM UniPHY 400MHz x72

Design Example - Stratix III DDR2 SDRAM UniPHY 400MHz x72


Last Major Update

Initial Release – Jan 2012 – Stratix III DDR2 SDRAM x72 300 MHz, Quartus II v11.1, DDR2 SDRAM Controller with UniPHY.

 

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to design a 72-bit wide, 300-MHz DDR3 SDRAM interface working with a Stratix III FPGA using a 72-bit wide 1-Gb Micron MT9HTF12872AY-800E 400-MHz DDR2 SDRAM DIMM. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the UniPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process. Volume 6 of the External Memory Interface Handbook should be used for a more thorough walkthrough. 

 

The UniPHY IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 SDRAM functionality.

 

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
Quartus versionQuartusII v11.1
FPGAEP3SL150F1152C2
KitStratix III FPGA Demonstration Kit
Memory deviceDDR2 SDRAM (Micron MT9HTF12872AY-800E)
Memory speed400MHz
Memory topologyx72-bit, DDR2 unbuffered DIMM
IP usedDDR2 SDRAM Controller II with UniPHY IP and generated example top Quartus project

 

Lab Steps

The lab uses Quartus II v11.1 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features.


Four files have been pre-designed for this lab to save time.

• A pin location assignments tcl script (S3_Host_DDR2_PinLocations.tcl)

• A signal tap file for debug of the interface design that has been created

• A board trace model assignments script (S3_Host_DDR2_BTModels.tcl)

• A virtual pins assignments script for this design (S3_Host_ddr2_exdriver_vpin.tcl)

 

A Quartus archive for the final project is also included for reference.

Files for this lab are located in this zip file – emi_uniphy_ddr2_siii

Create a new folder for the project and place the files in it.


Design Generation 

1. Use the Megawizard Plug-in Manager to generate a DDR2 SDRAM Controller with UniPHY

Start Quartus, open MegaWizard Plug-In Manager and create a new variation 

• In the Megawizard GUI, set device family to be Stratix III 

• The IP is located under the folders Interfaces/External Memory/DDR2 SDRAM, choose DDR2 SDRAM High Performance Controller with UniPHY v11.1

• If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type 

• For the name of the output file, browse to the folder you created above, give the instance the name “ddr2_uniphy”, click Open, click Next to open the IP GUI 


2. Set parameters for Memory Controller with UniPHY

• PHY Settings Tab

1. Set Speed grade to 2.

2. Set Memory clock frequency to 300 MHz

3. Set PLL reference clock frequency to 50 MHz.

4. Select Half for Full- or half-rate Avalon-MM interface.

5. Select Skip calibration for Auto-calibration mode under Example Testbench Simulation Options.

 

• Memory Parameters Tab

1. Select Unbuffered DIMM for Memory format.

2. Select 400 MHz for Memory device speed grade,

3. Type 72 for Total interface width.

4. Select 1 for Number of slots and Number of chip select per slot, select 1.

5. Select 3 for Number of clocks per chip select.

6. Type 10 for Row address width and Column address width.

7. Type 3 for Bank address width.

8. Select 6 for Memory CAS latency setting under Memory Initialization Options, 

9. Select Full for Output drive strength setting.

10. Select 75 for Memory on-die termination (ODT) setting.  


• Board Settings Tab 

1. Set the Board Skews parameters to the specific values shown in table below under Board Skews:

Slew Rate ParameterSkew (ns)
Minimum delay difference between CK and DQS0.098
Maximum delay difference between CK and DQS0.151
Maximum skew within DQS group0.000
Maximum skew between DQS groups0.053
Average delay difference between DQ and DQS0.000
Maximum skew within address and command bus0.155
Average delay difference between address and command and CK0.490


• Controller Settings Tab 

1. Set 64 for Maximum Avalon-MM burst length under Avalon Interface


3. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their UniPHY IP configuration on hardware. 

• Open the example project located in <variation_name>_example_design/example_project. If the device you are using does not match the device in the example project, change the device in the project. 


4. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step.


5. Assign the pin and DQ group settings 

Run the tcl script ddr2_uniphy_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard 

• Verify in the Assignment Editor that pin assignments have been created successfully 


6. Assign the pin locations 

Pin locations for external memory systems are not automatically created. 

• Run the S3_Host_DDR2_PinLocations.tcl script to assign pin locations for the targeted kit 

• Run the s3_Host_ddr2_exdriver_vpin.tcl script to assign virtual pins

• Verify in Pin Planner or Assignment Editor that pin locations have been created successfully


7. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.


Design Analysis 

1. Timing Analysis results 

• In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

- Check the summary at the bottom of that report

- Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.


2. On board debug with Signal Tap 

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation 

• Program the kit FPGA with the .sof 

• Run Signal Tap Analysis

- Restart the driver

- Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.

- Also check that calibration was successful and that the PLL is locked 


Design Simulation 

The Quartus II software creates a complete design example for functional simulation in the <variation_name>_example_design/simulation/ directory. To run the RTL simulation, perform the following steps:

• Open the generated example project for the design example simulation, <variation_name>_example_design/simulation/<variation_name>_ example_sim.qpf. 

• Select Tools -> Tcl Scripts... -> generate_sim_verilog_example_design.tcl and click "Run". 

• Open Modelsim. 

• Move into the directory ./verilog/mentor or ./vhdl/mentor.

• Start Modelsim and run the "run.do" script: in Modelsim, enter "do run.do".

• The simulation will stop once the test complete signal goes high in the test bench 

• CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset 

• Observe the results in the ModelSim Wave window


 

Notes/Comments


Update History

Initial Release – Jan 2012 – Stratix III DDR2 SDRAM x72 300 MHz, Quartus II v11.1, DDR2 SDRAM Controller with UniPHY, Stratix III FPGA Development Kit. 

 

See Also

1. List of designs using Altera External Memory IP 


External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

 

Key Words

UniPHY, DDR3 SDRAM, Design Example, External Memory , Stratix III, SIII

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‎06-27-2019 04:24 PM
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