Design Example - Stratix III DDR3 SDRAM ALTMEMPHY 533MHz x72

Design Example - Stratix III DDR3 SDRAM ALTMEMPHY 533MHz x72

Last Major Update

Initial Release – December 2010 – Stratix III DDR3 SDRAM x72 533MHz, Quartus II v9.1, DDR3 SDRAM High Performance Controller II with ALTMEMPHY, Stratix III Memory Demonstration Kit.

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a DDR3 SDRAM interface working with a Stratix III FPGA using a single Micron MT9JSF12872AY-1G1BZES unbuffered DIMM on the Stratix III Memory Demonstration Kit. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the ALTMEMPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process.

The lab creates a 72 bit 533MHz DDR3 SDRAM external memory PHY and controller using Altera’s DDR3 SDRAM High Performance Controller II with ALTMEMPHY IP. The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 SDRAM functionality

Design Specifications

The table below lists the specifications for this design:

Attribute	Specification
Quartus version	QuartusII v9.1
FPGA	EP3SL150F1152-C2ES
Kit	Stratix III Memory Demonstration Kit
Memory device	DDR3 SDRAM (Micron MT9JSF12872AY-1G1BZES)
Memory speed	533MHz
Memory topology	x72-bit, 1152-Mbps DDR3 unbuffered DIMM
IP used	DDR3 SDRAM High Performance Controller II with ALTMEMPHY IP and generated example top Quartus project

Lab Steps

The lab uses Quartus II v9.1 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

Four files have been pre-designed for this lab to save time.

• A pin location assignments tcl script (S3_MB1_DDR3_PinLocations.tcl)

• A signal tap file for debug of the interface design that has been created

• A board trace model assignments script (S3_MB1_DDR3_BTModels.tcl)

• A virtual pins assignments script for this design (S3_MB1_ddr3_exdriver_vpin.tcl)

A Quartus archive for the final project is also included for reference.

Files for this lab are located in this zip file – emi_ddr3_siii.zip

Create a new folder for the project and place the files in it

Design Generation

1. Use the Megawizard Plug-in Manager to generate a DDR3 SDRAM High Performance Controller

Copy the memory parameters files, S3MB1_Derated (Micron MT9JSF12872AY-1G1BZES).xml, to your <installation directory>\91\ip\ddr3_high_perf\lib directory.

Start Quartus, open MegaWizard Plug-In Manager and create a new variation.

In the Megawizard GUI, set device family to be Stratix III
The IP is located under the folders Interfaces/External Memory/DDR3 SDRAM, choose DDR3 SDRAM High Performance Controller v9.1
If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type
For the name of the output file, browse to the folder you created above, give the instance the name “ddr3_dimm”, click Open, click Next to open the IP GUI

2. Set parameters for Memory Controller with ALTMEMPHY

General Settings Tab

Set Speed grade to 2
Set PLL reference clock frequency to 100 MHz.
Set Memory clock frequency to 533 MHz
For Memory Presets, select S3MB1_Derated (Micron MT9JSF12872AY-1G1BZES), which gives a 72-bit wide, 1,152-Mbps 533-MHz
Change tIS, tIH, tDS, and tDH parameters in the Memory Preset with the derated parameters after running board simulation

■ Address and command = 1.5 V/ns

■ CLK and CLK# = 3 V/ns (differential)

■ DQ = 2 V/ns

■ DQS = 3 V/ns (differential)

Hence, the correct tIS, tIH, tDS, and tDH values for this design are:

■ tIS = tISb + ΔtIS + (VIHAC – VREF)/address and command rising slew rate

=125 + 59 + 175/1.5 = 301 ps

■ tIH = tIHb + ΔtIH + (VREF – VILDC)/address and command rising slew rate

= 200 + 34 + 100/1.5 = 301 ps

■ tDS = tDSb + ΔtDS + (VIHAC – VREF)/DQ rising slew rate

= 25 + 88 + 175/2 = 201 ps

■ tDH = tDHb + ΔtDH + (VREF – VILDC)/DQ rising slew rate

= 100 + 50 + 100/2 = 200 ps

6. To set the ODT settings for the DDR3 SDRAM interface on your board, in the Preset Editor dialog box, select Memory Initialization Options.

7. In the Memory Initialization Options dialog box, perform the following steps:

a. For Output driver impedance, select RZQ/7 (which is 34).

b. For Dynamic ODT (Rtt_WR) value, select Dynamic ODT off.

c. For ODT Rtt nominal value, select RZQ/4 (which is 60).

d. Click OK to apply the settings and exit the dialog box.

PHY Settings Tab

Turn on Enable dynamic parallel on-chip termination (OCT) option under Advanced PHY
Under Address/Command Clock Settings, for Dedicated clock phase type 240.
Under Board Timing Parameters, for Board skew type 20 ps.

Controller Settings Tab

1. Set High Performance Controller II as Controller Architecture for higher efficiency and advanced features.

2. Under Efficiency, select the specified values for the following options:

a. For Command Queue Look-Ahead Depth, select 6.

b. For Local-to-Memory Address Mapping, select CHIP-ROW-BANK-COL.

c. For Local Maximum Burst Count, select 4.

3. Click Next.

4. Turn the Generate simulation model option.Click “Finish” to start IP generation. Check important messages during generation. After IP is successfully generated, click Exit to close GUI. The ALTMEMPHY megafunction is instantiated automatically.

3. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their ALTMEMPHY IP configuration on hardware.

Open the top-level entity file, <variation_name>_example_top.v or vhd
On the Project menu click Set as Top-Level Entity

4. Perform Analysis and Synthesis

This step is required so Quartus can determine the names of the external ports connected to the ALTMEMPHY for when the I/O assignments are created in the next step.

5. Set Optimization Technique

This step is required to ensure the remaining unconstrained paths are routed with the highest speed and efficiency. To set the optimization technique, perform the following steps:

On the Assignments menu, click Settings
Select Analysis & Synthesis Settings
Select Speed under Optimization Technique. Click OK

6. Set Fitter Effort

To set the fitter effort, perform the following steps:

On the Assignments menu, click Settings
Select Fitter Settings
Turn on Optimize hold timing and select All Paths
Turn on Optimize multi-corner timing
Select Standard Fit (highest effort) under Fitter effort
Click OK

7. Add Timing Constraints

To add timing constraints, perform the following steps:

On the Assignments menu click Settings.
In the Category list, expand Timing Analysis Settings, and select TimeQuest
Timing Analyzer.
Select the <variation_name>_phy_ddr_timing.sdc file and click Add.
Click OK.

8. Assign the pin and DQ group settings

Run the tcl script ddr3_dimm_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard

Verify in the Assignment Editor that pin assignments have been created successfully

9. Assign the pin locations

Pin locations for external memory systems are not automatically created.

Run the S3_MB1_DDR3_PinLocations.tcl script to assign pin locations for the targeted kit
Run the S3_MB1_ddr3_exdriver_vpin.tcl script to assign virtual pins
Verify in Pin Planner or Assignment Editor that pin locations have been created successfully

10. Assign I/O Standards

To assign the I/O standards, perform the following steps:

On the Assignments menu, click Assignment Editor.
Specify LVDS as the I/O standard for clock_source.
Specify 2.5 V as the I/O standard for global_reset_n.

11. Enter board trace models

Run the S3_MB1_DDR3_BTmodels.tcl script to enter the board trace model for the targeted kit

12. Advanced I/O Timing

ALTMEMPHY-based designs assume that the memory address and command signals are matched length to the memory clock signals. Typically, this length match is not true for DIMM-based designs. You should verify the difference in your design. For the Stratix III development board fitted with the Micron MT9JSF12872AY-1G1BZES DIMM, the address and command signals remain asserted 300 ps shorter than the clock signals.

Open the ddr3_dimm_phy_ddr_timing.sdc file in a text editor and find the following line:

set(additional_addresscmd_tpd) 0.000

Change the line to the following text:

set(additional_addresscmd_tpd) -0.300

Save the file

13. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.

Design Analysis

1. Timing Analysis results

In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

- Check the summary at the bottom of that report

- Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.

8/88/SIII_DDR3_timing_report.JPG ( SIII DDR3 timing report.JPG - click here to view image )

2. On board debug with Signal Tap

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation

Program the kit FPGA with the .sof
Run Signal Tap Analysis
- Restart the driver

- Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.

- Also check that calibration was successful and that the PLL is locked

Design Simulation

Run EDA RTL Simulation from Tools Menu – Run EDA Simulation Tool -> EDA RTL Simulation

- The simulation will stop once the test complete signal goes high in the test bench

- CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset

- Observe the results in the ModelSim Wave window

Notes/Comments

For a list of supported and unsupported features in the DDR3 SDRAM Controller with ALTMEMPHY, refer to the DDR3 SDRAM Controller with ALTMEMPHY IP User Guide. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

Update History

Initial Release – December 2010 – Stratix III DDR3 SDRAM x72 533MHz, Quartus II v9.1, DDR3 SDRAM High Performance Controller II with ALTMEMPHY, Stratix III Memory Demonstration Kit.

External Links

1. Altera's External Memory Interface Solutions Center

2. Altera's External Memory Interface Handbook

Key Words

ALTMEMPHY, DDR3 SDRAM, Design Example, External Memory , Stratix III, SIII