Community
cancel
Showing results for 
Search instead for 
Did you mean: 

Design Example - Stratix III QDRII+ SRAM ALTMEMPHY 400MHz x18

Design Example - Stratix III QDRII+ SRAM ALTMEMPHY 400MHz x18


Last Major Update

 February 2010 - Stratix III QDRII+ SRAM x18 400MHz, Quartus II v8.0, ALTMEMPHY Stratix III FPGA development kit.

 

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a QDR II+ SRAM interface working with a Stratix III FPGA using QDR II+ SRAM device on the Stratix III FPGA development kit. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the ALTMEMPHY. The lab will not cover any of the steps in detail but simply show an overview of the design process. Volume 6 of the External Memory Interface Handbook should be used for a more through walkthrough. 

The lab creates a 18-bit 400MHz QDR II+ SDRAM external memory PHY and controller using ALTMEMPHY. The design contains the following elements which will be used to demonstrate the QDR II+ SRAM functionality:


1. QDR II+ driver, 

2. a LFSR to generate data which will be written in the QDR II+ SRAM memory 

3. a comparator to compare read back data with the data written to the memory

4. a counter to generate address


The design writes to 100 addresses in QDR II+ SRAM memory and then reads it back. The read back data is compared with the data written and the pass or fail signal (pof) is asserted accordingly. 


Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
Quartus versionQuartusII v8.0
FPGAEP3SL150F1152C2
KitStratix III FPGA development kit
Memory deviceQDR II+ SRAM (Cypress CY7C1263V18)
Memory speed400MHz
Memory topology 18-bit, 36 Mbit, 4-word burst
IP usedALTMEMPHY

 

Lab Steps

The lab uses Quartus II v8.0 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features.


Two files have been pre-designed for this lab to save time.

  • A pin location assignments tcl script
  • A signal tap file for debug of the interface design that has been created


A Quartus archive for the final project is also included for reference.

Files for this lab are located in this zip file – an461_example.zip

Create a new folder for the project and place the files in it 


Design Generation

1. Use the Megawizard Plug-in Manager to generate a ALTMEMPHY IP

Start Quartus, open MegaWizard Plug-In Manager and create a new variation

  • In the Megawizard GUI, set device family to be Stratix III
  • The IP is located under the folders I/O, choose ALTMEMPHY
  • If your license for ModelSim can not support multiple HDL languages then chose verilog as output file type
  • For the name of the output file, browse to the folder you created above, give the instance the name (for example “fred”) and click Next to open the IP GUI 

2. Set parameters for ALTMEMPHY 

On the right of the GUI are some Memory Presets, click QDRII+ 1M ×18 BL4 CL2.5 400 MHz and apply 

• Memory Settings Tab 

- Set Speed Grade to 2 

- Set Memory Clock Frequency to 400MHz 

- Set PLL Reference Clock Frequency to 125MHz 

- Select Modify parameters options to modify all the parameters. Set the Address width to 19. Verify that the other memory timing parameters match the QDRII+ SRAM datasheet as well. After making all necessary updates, select OK. This will create a custom memory preset with your selections.

• PHY Settings Tab 

- Turn on Use differential DQS under Advanced PHY 

- Turn on the Enable dynamic parallel on-chip termination (OCT) option

- Under Address/Command Clock Settings, for Dedicated clock phase type 240. 

- Under Board Timing Parameters, for Board skew type 20 ps.


• Controller Interface Settings Tab 

- Click Next

• Turn on the Generate simulation model option

• Click “Finish” to start IP generation. Check important messages during generation. After IP is successfully generated, click Exit to close GUI .


3. Create Top-Level Entity

The Megawizard doesn’t generate a Quartus example top project. You should connect the local signals of the memory interface from the PHY to the logic that will access the memory in your top-level design.

4. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the ALTMEMPHY for when the I/O assignments are created in the next step 

5. Add Timing Constraints 

To add timing constraints, perform the following steps:

• On the Assignments menu click Settings.

• In the Category list, expand Timing Analysis Settings, and select TimeQuest

• Timing Analyzer.

• Select the <variation_name>_ddr_timing.sdc file and click Add.

• Click OK.

6. Assign the pin and DQ group settings 

Run the tcl script fred_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard 

• Verify in the Assignment Editor that pin assignments have been created successfully

7. Assign the pin locations. Pin locations for external memory systems are not automatically created. 

• Run the SIII_host_qdrii_pin_location.tcl script to assign pin locations for the targeted kit 

• Verify in Pin Planner or Assignment Editor that pin locations have been created successfully 

8. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.

 

Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 04:31 PM
Updated by:
 
Contributors