Initial Release - Jan 2012 – Stratix III RLDRAM II x36 400MHz, Quartus II v11.1, RLDRAM II Controller with UniPHY, Stratix III Memory internal board.
This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a RLDRAM II interface working with a Stratix III FPGA using a single component on the Stratix III internal memory board. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the UniPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process. Volume 6 of the External Memory Interface Handbook should be used for a more thorough walkthrough.
The lab creates a 36bit 400MHz RLDRAM II external memory PHY and controller using Altera’s RLDRAM II Controller with UniPHY IP. The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the RLDRAM II functionality
The table below lists the specifications for this design:
|Quartus version||QuartusII v11.1|
|Kit||Stratix III internal memory board|
|Memory device||RLDRAM II (Micron MT49H16M36HT-18)|
|Memory topology||single component, x36|
|IP used||RLDRAM II Controller with UniPHY and generated example top Quartus project|
The lab uses Quartus II v11.1 and has Modelsim for simulation. The lab assumes the reader is a competent user of these tools and many of their features.
Three files have been pre-designed for this lab to save time.
A Quartus archive for the final project is also included for reference.
Files for this lab are located in this zip file – StratixIII_UniPHY_RLDRAMII.zip
Create a new folder for the project and place the files in it
1. Use the Megawizard Plug-in Manager to generate a RLDRAM II Controller with UniPHY
2. Set parameters for Memory Controller with UniPHY
On the right of the GUI are some Memory Presets, click Micron MT49H16M36HT-18 and apply
- Set Speed Grade to 2
- Set Memory Clock Frequency to 400MHz
- Set PLL Reference Clock Frequency to 100MHz
- For Full or half rate on Avalon-MM interface, select Half. This option allows you to choose between the full-rate and half-rate controller, and define the bus data width between the controller and the PHY.
- For Additional Address/Command clock phase, select 0.
- Select 128 for maximum Avalon-MM burst length
- Select 1.8V HSTL for I/O standard
- Turn on Master for PLL/DLL sharing to instantiate its own PLL. If the Master for PLL/DLL sharing option is disabled, the PLL clock shares with other identical UniPHY core.
-Under Example Testbench Simulation Options, turn on Skip memory initialization to reduce simulation time.
- Select tRC=6, tRL=6, tWL=7, f=400–175MHz for Memory Mode Register Configuration
- Keep the rest of this page to default
- In the Board Settings tab, set the Setup and Hold Derating parameters to the specified values below:
tAS Vref to CK/CK# Crossing: 25ps
tAS VIH MIN to CK/CK# Crossing: -100ps
tAH CK/CK# Crossing to Vref: 13ps
tAH CK/CK# Crossing to VIH MIN: -50ps
tDS Vref to CK/CK# Crossing: 11ps
tDS VIH MIN to CK/CK# Crossing: -100ps
tDH CK/CK# Crossing to Vref: 6ps
tDH CK/CK# Crossing to VIH MIN: -50ps
- Set INI parameters to 0ps for single chip select.
- Set the Board Skews parameters to the specified values below:
Minimum delay difference between CK and DK: -55ps
Maximum delay difference between CK and DK: 0ps
Maximum delay difference between devices: 0ps
Maximum skew within DK group: 45ps
Maximum skew between DK groups: 32ps
Average delay difference between Address/Command and CK: 87ps
Average delay difference between Data and DK: 61ps
Average delay difference between Data and QK: -32ps
Maximum skew within Address/Command bus: 93ps
3. Open the example project generated by the Megawizard
The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their UniPHY IP configuration on hardware.
4. Perform Analysis and Synthesis
This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step
5. Assign the pin and DQ group settings
Run the tcl script rldram_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard
6. Assign the pin locations for external memory systems.
7. Do a Full Compile
This should take about 10 minutes depending on the compiling PC.
8. Perform RTL Simulation(optional)
1. Timing Analysis results
- Check the summary at the bottom of that report
- Check that all set up and hold timings pass
Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.
2. On board debug with Signal Tap
Open the Signal Tap file and reset the .sof file to the one just created with the full compilation
- Restart the driver
- Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.
- Also check that calibration was successful and that the PLL is locked
The Quartus II software creates a complete design example for functional simulation in the <variation_name>_example_design/simulation/ directory. To run the RTL simulation with NativeLink, perform the following steps:
1. Initial Release - Jan 2012 - SIII RLDRAM II x36 400MHz, QuartusII v11.1, UniPHY, SIII FPGA memory internal board.
UniPHY, RLDRAM II, Design Example, External Memory
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