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Design Example - Stratix IV DDR3 SDRAM UniPHY 400MHz x8

5. Adding Constraints 

After generating the DDR3 SDRAM Controller with UniPHY, the UniPHY IP generates the constraint files for the design. You need to apply these constraints to the design before compilation.


Setting Pins 

Set the unused pin and device voltage correctly before adding the constraint and pin assignment. Perform the following steps to set the device voltage and unused pin:

a. On the Assignment menu, select Device and click Device and Pin Options.

b. Click the Unused Pins tab, and for Reserve all unused pins select As input tri-stated with weak pull-up.

c. Click the Voltage tab, and for Default I/O standard select the same VCCIO voltage as the chosen SDRAM interface; for DDR3 SDRAM select 1.5 V.

d. Click OK.


Assigning I/O Standards 

To assign I/O standards, follow these steps:

a. On the Assignment menu, click Assignment Editor.

b. Specify LVDS as the I/O standard for pll_ref_clk.


Adding the Quartus II IP File 

When you instantiate an SDRAM controller with UniPHY, it automatically generates a Quartus II IP File (.qip), system.qip. To add .qip, follow these steps:

a. On the Project menu, click Add/Remove Files in Project.

b. Browse to the <project_name>/synthesis directory, and add <memory_instance>.qip.

c. Click OK.


Setting Optimization Technique 

To ensure that the remaining unconstrained paths are routed with the highest speed and efficiency, set the optimization technique. To set the optimization technique, follow these steps:

a. On the Assignments menu, click Settings.

b. Select Analysis & Synthesis Settings.

c. Select Speed under Optimization Technique.

d. Click OK.


Setting Fitter Effort 

To set the Fitter effort, follow these steps:

a. On the Assignments menu click Settings.

b. In the Category list, expand Fitter Settings.

c. Turn on Optimize Hold Timing and select All Paths.

d. Turn on Optimize Multi-Corner Timing.

e. Select Standard Fit under Fitter Effort.

f. Click OK.

Design Analysis

1. Timing Analysis results

In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder 

- Check the summary at the bottom of that report

- Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.

 

2. Incorporate the Nios II Eclipse 

You can now add test code to the project Nios II processor and use this program to run some simple tests. When doing memory tests, you must read and write from the external DDR3 SDRAM and not from cached memory. The following two methods avoid using Nios II cached memory:

■ Use a Nios II processor that does not have cache memory, like the Nios II/s used in this example project.

■ Use the alt_remap_uncached function.

 

Launching the Nios II Eclipse 

To launch the Nios II Eclipse, follow these steps:

1. On the Windows Start menu, point to All Programs, Altera, Nios II EDS <version>, and then click Nios II <version> Software Build Tool for Eclipse.

2. On the File menu, point to Switch Workspace, click Browse, and select your project directory.

3. On the File menu, point to New and click Project.

4. Select Nios II Application and BSP from Template, and click Next.

5. Select Blank Project under Project Templates, browse and locate the SOPC Information File, <project_name>.sopcinfo, and type siv_ddr3_uniphy as project name under the Application

   project.

6. Click Next and click Finish.

7. In Windows Explorer, drag Altera-supplied DDR_TEST.c to the siv_ddr3_uniphy directory.This program consists of a simple loop that takes commands from the JTAG UART

   and executes them. Table below shows the commands that are sent to the Nios II C code.The commands must be in the following format and the switches A, B, C, and D must

   be entered in upper case. Both address and data strings must always be 8 characters long.

 

Command

FormatDescriptionExample
Switch ASwitch | DataControls the LEDs.A000000FF. The last two bytes control all eight LEDs. The LEDs are active low on the board.
Switch BSwitch | Address | DataPerforms a single write to an address offset location in memory.Enter B, followed by 00000001, then 12345678, writes 12345678 at SDRAM memory address location 00000001.
Switch CSwitch | AddressPerforms a single read to an address offset location in memory.Enter C, followed by 00000001, reads the contents of the memory at SDRAM address offset location 00000001.
Switch DSwitch | From Address | To AddressPerforms an incremental write to the first address location, followed by a DMA transfer from the first address location to the second address location. The burst is afixed length of 512 words or 2048 bytes.D0802100000000000 loads the DMA read memory with the incrementing pattern, then DMA  transfers it to the SDRAM high-performance controller.

The Qsys Component Address figure shows that the Qsys component address locations can be obtained directly from the Qsys Window.


Setting Up the Project Settings 

To set up the Nios II project settings, perform the following steps:

1. In the Project Explorer tab, right-click <project_name> and select Nios II, and click BSP Editor to launch the Nios II BSP Editor.

2. To optimize the footprint size of the library project, in the Main tab, point to Settings, and turn on enabled_reduced_device_drivers.

3. To reduce the memory size allocated for the system library, for Max file descriptors, type 4.

4. In the Linker Script tab, select onchip_mem as the linker region name for .bss, .heap, .rodata, .rwdata, .stack, and .text. The Nios II Project Settings Figure shows the Nios II 

   BSP Editor dialog box.

5. Click Generate.

 

3. Verifying Design on a Development Platform 

The SignalTap II Embedded Logic Analyzer shows read and write activity in the system.

To add the SignalTap II Embedded Logic Analyzer, perform the following steps:

1. On the Tools menu, click SignalTap II Logic Analyzer.

2. In the Signal Configuration window next to the Clock box, click ... (Browse Node Finder).

3. Type *phy_clk in the Named box, for Filter select SignalTap II: pre-synthesis and click List.

4. Select ddr3_qsys:inst|ddr3_qsys_uniphy_ddr3:uniphy_ddr3|ddr3_qsys_uniphy_ddr3_p0:p0|phy_clk in Nodes Found and click > to add the signal to Selected Nodes.

5. Click OK.

6. Under Signal Configuration, specify the following settings:

■ For Sample depth, select 512

■ For RAM type, select Auto

■ For Trigger flow control, select Sequential

■ For Trigger position, select Center trigger position

■ For Trigger conditions, select 1

7. On the Edit menu, click Add Nodes.

8. Search for specific nodes by typing *avl_* in the Named box, for Filter select SignalTap II: pre-synthesis and click List.

9. In Nodes Found, select the following nodes and click > to add to Selected Nodes:

■ avl_addr

■ avl_rdata

■ avl_rdata_valid (alternative trigger to compare read/write data)

■ avl_read_req

■ avl_wdata

■ avl_write_req (trigger)

10. On the Edit menu, click Add Nodes again.

11. Search for specific nodes by typing *controller_inst|itf*data_valid in the Named box, for Filter select SignalTap II: pre-synthesis and click List.

12. In Nodes Found, select the following nodes and click > to add to Selected Nodes:

■ itf_rd_data_valid

■ itf_wr_data_valid

13. Click OK.

14. To reduce the SignalTap II logic size, turn off Trigger Enable on the following buses:

■ avl_addr

■ avl_rdata

■ avl_wdata

15. Right-click Trigger Conditions for the avl_write_req signal and select Rising Edge.The SignalTap II Embedded Logic Analyzer Figure shows the completed SignalTap II Embedded Logic Analyzer.

16. On the File menu, click Save, to save the SignalTap II .stp file to your project.


Compiling the Project 

Once you add signals to the SignalTap II Embedded Logic Analyzer, recompile your design, on the Processing menu, click Start Compilation.


Verifying Timing 

Once the design compiles, ensure that the TimeQuest timing analysis passes successfully. In addition to this FPGA timing analysis, check your PCB or system SDRAM timing. 

To run timing analysis, run the <variation name >_phy_report_timing.tcl script by performing the following steps:

1. On the Tools menu, click Tcl Scripts.

2. Select <variation name>_uniphy_ddr3_p0_report_timing.tcl and click Run.


Connecting the Development Board 

Connect the Stratix IV development board to your computer. 


Downloading the Object File 

On the Tools menu, click SignalTap II Logic Analyzer. The SignalTap II dialog box appears. The SRAM Object File (SOF) Manager should contain the <your project name>.sof file. To add the correct file to the SOF Manager, perform the following steps:

1. Click ... to open the Select Program Files dialog box, refer to The Install the SRAM Object File in the SignalTap II Dialog Box Figure

2. Select <your project name>.sof.

3. Click Open.

4. To download the file, click the Program Device button.

 

Verifying Design with Nios II 

Right-click on project folder, point to Run As, and click Nios II Hardware for the Nios II C/C++ Eclipse to compile the example test program. 

If you have more than one JTAG download cable connected to your computer you may see an JTAG error. If you receive a JTAG error, perform the following steps: 

1. From the Nios II Eclipse, on the Run menu click RUN.

2. Click the Target Connection tab and correct the JTAG cable connection, refer to the JTAG Download Target Connection Settings Figure.

3. Right click on <target>_project, point to Run As, and click Nios II Hardware.


Testing the System 

Perform the following tests to verify your system is operating correctly. 


Test 1: Setting SignalTap II Trigger to avl_write_req 

Use the SignalTap II Embedded Logic Analyzer to capture write activity. To show write activity, follow these steps:

1. In the Setup tab, select to trigger on a rising edge of avl_write_req, refer to The Set Trigger for avl_write_req Signal Figure.

2. Click Run Once Analysis to capture the write request.

3. Type the following command in the Nios II command console: B123456780000001

4. Return to the SignalTap II Embedded Logic Analyzer window and check that at time 0 the following occur (refer to the Waveform for Write Request Figure):

■ avl_write_req signal goes high for a single cycle

■ avl_wdata shows 12345678h

■ avl_address shows 000001h


Test 2: Setting SignalTap II Trigger to avl_read_req 

Use the SignalTap II Embedded Logic Analyzer to capture read activity. To show read activity, perform the following steps:

1. In the Setup tab, select to trigger on a rising edge of avl_read_req, refer to the Set Trigger for avl_read_req Signal Figure.

2. Click Run Once Analysis to capture the read request

3. Type the following command in the Nios II command console: C00000001

4. Return to the SignalTap II Embedded Logic Analyzer window and check that at time 0 the following occur (refer to theWaveform for Read Request Figure):

■ avl_read_req signal goes high

■ avl_address shows 000001h

Several clock cycles later, depending on the system read latency:

■ avl_rdata_valid goes high for one cycle

■ avl_rdata shows 12345678h


Test 3: Testing DMA Read and Write Operation 

Use the SignalTap II Embedded Logic Analyzer to capture DMA read and write activity. To show activity, follow these steps:

1. In the Setup tab, select to trigger on a rising edge of avl_write_req and on a falling edge of avl_read_req, refer to the Set Trigger for avl_write_req and avl_read_req Signal Figure

2. Click Run Once Analysis to capture the write request.

3. Type the following command in the Nios II command console: D802100000000000

4. Return to the SignalTap II Embedded Logic Analyzer window and check that at time 0, the following occur (refer to the Waveform for Continuous Read and Write Activity Figure):

■ avl_write_req and avl_read_req signal goes high for multiple cycles

■ avl_wdata shows 03020100h followed by 07060504h and so on

■ avl_address shows 000000h followed by 000001h and so on

The current avl_address increases by 1 compared to the avl_address of previous read or write request. The write data is first to last, most significant byte (MSB) to the least 

significant byte (LSB) count format. For example, a count of 00,01,02,03 = 03020100h. 

 

Notes/Comments

For a list of supported and unsupported features in the DDR2 SDRAM Controller with UniPHY, refer to the DDR2 and DDR3 SDRAM Controller with UniPHY User Guide. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.


Update History 

Initial Release – July 2011 – Stratix IV DDR3 SDRAM x16 400-MHz, Quartus II v11.0, DDR3 SDRAM Controller with UniPHY using Qsys.

Update – December 2011 – Stratix IV DDR3 SDRAM x16 400-MHz, Quartus II v11.1, DDR3 SDRAM Controller with UniPHY using Qsys. 

 

See Also

1. List of designs using Altera External Memory IP


External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook


Key Words

UniPHY, DDR3 SDRAM, Design Example, External Memory, Stratix IV, SIV, Qsys

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