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Design Example - Stratix IV DDR3 SDRAM UniPHY 533MHz x64

Design Example - Stratix IV DDR3 SDRAM UniPHY 533MHz x64



 

Contents

 [hide

Last Major Update

Initial Release – Dec 2011 – Stratix IV DDR3 SDRAM x64 533 MHz, Quartus II v11.1, DDR3 SDRAM Controller with UniPHY.

 

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to design a 64-bit wide, 533-MHz DDR3 SDRAM interface working with a Stratix IV FPGA using a 64-bit wide DDR3 SDRAM interface comprises four MT41J64M16LA-15E DDR3 SDRAM components. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the UniPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process. Volume 6 of the External Memory Interface Handbook should be used for a more thorough walkthrough. 

 

The UniPHY IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 SDRAM functionality.

 

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
Quartus versionQuartusII v11.1
FPGAEP4SGX230KF40C2
KitStratix IV GX FPGA Demonstration Kit
Memory deviceDDR3 SDRAM (Micron MT41J64M16LA-15E)
Memory speed533MHz
Memory topologyx64-bit, 4 DDR3 SDRAM components with fly-by topology
IP usedDDR3 SDRAM Controller II with UniPHY IP and generated example top Quartus project

 

Lab Steps

The lab uses Quartus II v11.1 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features.


Three files have been pre-designed for this lab to save time.

• A pin location assignments tcl script (siv_gx_ddr3bot_pin_location.tcl)

• A signal tap file for debug of the interface design that has been created

• A board trace model assignments script (S4_DDR3_BTModal.tcl)

 

A Quartus archive for the final project is also included for reference.

Files for this lab are located in this zip file – emi_uniphy_ddr3_siv

Create a new folder for the project and place the files in it.


Design Generation 

1. Use the Megawizard Plug-in Manager to generate a DDR3 SDRAM Controller with UniPHY

Start Quartus, open MegaWizard Plug-In Manager and create a new variation 

• In the Megawizard GUI, set device family to be Stratix IV 

• The IP is located under the folders Interfaces/External Memory/DDR3 SDRAM, choose DDR3 SDRAM High Performance Controller with UniPHY v11.1

• If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type 

• For the name of the output file, browse to the folder you created above, give the instance the name “ddr3”, click Open, click Next to open the IP GUI 


2. Set parameters for Memory Controller with UniHY

• PHY Settings Tab

1. Set Speed grade to 2.

2. Set Memory clock frequency to 533 MHz

3. Set PLL reference clock frequency to 50 MHz.

4. Select Half for Full- or half-rate Avalon-MM interface.

5. Select Skip calibration for Auto-calibration mode under Example Testbench Simulation Options.

 

• Memory Parameters Tab

1. Select Discrete Device for Memory format.

2. Select 666.66 MHz for Memory device speed grade,

3. Type 64 for Total interface width.

4. Select 1 for Number of slots and Number of chip select per slot, select 1.

5. Select 1 for Number of clocks per chip select.

6. Type 13 for Row address width.

7. Type 10 for Column address width.

8. Type 3 for Bank address width.

9. Select 8 for Memory CAS latency setting under Memory Initialization Options, 

10. Select RZQ/7 for Output drive strength setting.

11. Select 6 for Memory write CAS latency setting.

12. Select RZQ/4 for Dynamic ODT(Rtt_WR) setting. 


• Board Settings Tab 

1. Users should do board simulation for proper values in this page:

     - In the Board Settings tab, set the slew rate parameters to the specified values below:

          CK/CK# slew rate (Differential): 4V/ps

          Address and command slew rate: 1.5V/ns 

          DQS/DQS# slew rate (Differential): 3V/ns

          DQ slew rate: 1.5V/ns 


      - Set the Board Skews parameters to the specified values below:

         Maximum CK delay to DIMM/device: 618ps

          Maximum DQS delay to DIMM/device: 368ps

         Minimum delay difference between CK and DQS: 250ps 

          Maximum delay difference between CK and DQS: 378ps 

          Maximum skew within DQS group: 17ps

         Maximum skew between DQS groups: 128ps 

         Average delay difference between Address/Command and CK: 15ps 

          Average delay difference between DQ and DQS: 21ps

          Maximum skew within Address/Command bus: 72ps


• Controller Settings Tab 

1. Set 64 for Maximum Avalon-MM burst length under Avalon Interface


3. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their UniPHY IP configuration on hardware. 

• Open the example project located in <variation_name>_example_design/example_project. If the device you are using does not match the device in the example project, change the device in the project. 


4. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step.


5. Assign the pin and DQ group settings 

Run the tcl script ddr3_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard 

• Verify in the Assignment Editor that pin assignments have been created successfully 


6. Assign the pin locations 

Pin locations for external memory systems are not automatically created. 

• Run the Sivgx_ddr3_pin_locations.tcl script to assign pin locations for the targeted kit 

• Verify in Pin Planner or Assignment Editor that pin locations have been created successfully


7. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.


Design Analysis 

1. Timing Analysis results 

• In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

- Check the summary at the bottom of that report

- Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.


2. On board debug with Signal Tap 

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation 

• Program the kit FPGA with the .sof 

• Run Signal Tap Analysis

- Restart the driver

- Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.

- Also check that calibration was successful and that the PLL is locked 


Design Simulation 

The Quartus II software creates a complete design example for functional simulation in the <variation_name>_example_design/simulation/ directory. To run the RTL simulation, perform the following steps:

• Open the generated example project for the design example simulation, <variation_name>_example_design/simulation/<variation_name>_ example_sim.qpf. 

• Select Tools -> Tcl Scripts... -> generate_sim_verilog_example_design.tcl and click "Run". 

• Open Modelsim. 

• Move into the directory ./verilog/mentor or ./vhdl/mentor.

• Start Modelsim and run the "run.do" script: in Modelsim, enter "do run.do".

• The simulation will stop once the test complete signal goes high in the test bench 

• CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset 

• Observe the results in the ModelSim Wave window 


 

Notes/Comments


Update History

Initial Release – Dec 2011 – Stratix IV DDR3 SDRAM x64 533 MHz, Quartus II v11.1, DDR3 SDRAM Controller with UniPHY, Stratix IV GX FPGA Development Kit. 


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Last update:
‎06-25-2019 06:05 PM
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