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Design Example - Stratix IV QDR II SRAM UniPHY 400MHz x18

Design Example - Stratix IV QDR II SRAM UniPHY 400MHz x18

Last Major Update

Initial Release – July 2011 – Stratix IV QDR II+ SRAM x18 400 MHz, Quartus II v11.0, QDR II+ SRAM Controller with UniPHY.

Design Overview

 This design is meant as a demo style lab. It very briefly covers the steps required to design a 18-bit wide, 400-MHz QDR II+ SRAM interface working with a Stratix IV FPGA using a 18-bit wide 72-Mb Cypress CY7C1563KV18-400 400-MHz QDR II+ SRAM. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the UniPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process. The UniPHY IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the QDR II+ SRAM functionality.


Design Specifications

The table below lists the specifications for this design: 

Quartus versionQuartusII v11.1
Simulation toolModelSim_SE 10.0c
KitStratix IV GX FPGA development kit
Memory deviceQDR II+ SRAM (Cypress CY7C1563KV18-400)
Memory speed400MHz
Memory topologyX18-bit, QDR II+ SRAM component
IP used QDR II+ SRAM Controller with UniPHY IP


Lab Steps

The lab uses Quartus II v11.1 and assume the reader is a competent user of these tools and many of their features.

Three files have been pre-designed for this lab to save time.

• A pin location assignments tcl script (SIV_GX_qdrii_pin_location.tcl)

• A signal tap file for debug of the interface design that has been created

• A virtual pins assignments script for this design (SIV_GX_qdrii_exdriver_vpin.tcl)

A Quartus archive for the final project is also included for reference.

Files for this lab are located in this zip file -  emi_qdrii_plus_siv

Create a new folder for the project and place the files in it.

Design Generation

1. Use the Megawizard Plug-in Manager to generate a QDR II+ SRAM Controller with UniPHY

Start Quartus, open MegaWizard Plug-In Manager and create a new variation

• In the Megawizard GUI, set device family to be Stratix IV

• The IP is located under the folders Interfaces/External Memory/QDR II and QDR II+ SRAM, choose QDR II+ SRAM High Performance Controller with UniPHY v11.1

• If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type

• For the name of the output file, browse to the folder you created above, give the instance the name “qdrii_plus_siv”, click Open, click Next to open the IP GUI


2. Set parameters for Memory Controller with UniPHY

a. Set the parameter values for QDR II+ SRAM Controller with UniPHY as shown in the Parameter Values for QDR II+ SRAM Figure.

b Click Finish to generate your MegaCore function variation. The MegaWizard Plug-In Manager generates the following two example design projects.

  • Project for synthesis flow; obtain this file from the <variation_name>_example_design/example_project directory.
  • Project for simulation flow; obtain this file from the <variation_name>_example_design/simulation directory.

Each project includes full design RTL and the Quartus II project files (.qpf and .qsf) that you can use with minimal modifications.


3. Use Example Project

Open the example project located in<variation_name>_example_design/example_project. If the device you are using does not match the device in the example project, change the device in the project.

To change the device in the example project to the actual device you are targeting for your design, follow these steps:

  • On the Assignments menu, click Device.
  • Select the device of your choice.
  • Click OK.

4. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step.

5. Assign the pin and DQ group settings

Run the tcl script qdrii_plus_siv_example_if0_p0_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard. Verify in the Assignment Editor that pin assignments have been created successfully 

6. Assign the pin locations.

Pin locations for external memory systems are not automatically created. 

• Run the SIV_GX_qdrii_pin_location.tcl script to assign pin locations for the targeted kit 

• Run the SIV_GX_qdrii_exdriver_vpin.tcl script to assign virtual pins

• Verify in Pin Planner or Assignment Editor that pin locations have been created successfully

7. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.

Design Analysis

1. Timing Analysis results 

• In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder 

- Check the summary at the bottom of that report 

- Check that all set up and hold timings pass 

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.

2. On board debug with Signal Tap 

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation 

• Program the kit FPGA with the .sof 

• Run Signal Tap Analysis 

- Restart the driver 

- Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high. 

- Also check that calibration was successful and that the PLL is locked 

Design Simulation

This section describes RTL (functional) simulation. After you have generated your design, the Quartus II software creates a complete design example for functional simulation in the <variation_name>_example_design/simulation/ directory. This design example includes the driver, testbench, and the memory model that allows you to perform functional simulation on the design.The simulation example design is available for both Verilog and VHDL.Use the ModelSim-Altera simulator to perform the functional simulation.

To run the RTL simulation with NativeLink, perform the following steps:

  1. Open the generated example project for the design example simulation,<variation_name>_example_design/simulation generate_sim_example_design.qpf.
  2. Change the device in the design example to the actual device you are targeting for your design.
  3. To generate the Verilog example design, selectTools -> Tcl Scripts... -> generate_sim_verilog_example_design.tcl and click "Run". Alternatively, you can run "quartus_sh -t generate_sim_verilog_example_design.tcl" at Tcl console. The generated files will be found in the subdirectory "verilog". To generate the VHDL example design, select Tools -> Tcl Scripts... -> generate_sim_vhdl_example_design.tcl and click "Run".Alternatively, you can run "quartus_sh -t generate_sim_vhdl_example_design.tcl" at Tcl console. The generated files will be found in the subdirectory "vhdl".
  4. To simulate the example design using Modelsim AE/SE:   
  •  Start  Modelsim.
  •  Change directory to <variation_name>_example_design/simulation/verilog/mentor or <variation_name>_example_design/simulation/vhdl/mentor.                                        
  •  In transcript window, type "do" to run the file.The simulation will stop once the test complete signal goes high in the test bench.CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset.Observe the results in the ModelSim Wave window



For a list of supported and unsupported features in the QDR II and QDR II+ SRAM Controller with UniPHY, refer to the QDR II and QDR II+ SRAM Controller with UniPHY User Guide. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

Update History

Initial Release – July 2011 – Stratix IV QDR II+ SRAM x18 400 MHz, Quartus II v11.0, QDR II+ SRAM Controller with UniPHY, Stratix IV GX FPGA development kit

Update – November 2011 – Stratix IV QDR II+ SRAM x18 400 MHz, Quartus II v11.1, QDR II+ SRAM Controller with UniPHY.

See Also

1. List of designs using Altera External Memory IP 

External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

Key Words

UniPHY, QDR II+ SRAM, Design Example, External Memory , Stratix IV, SIV

Version history
Last update:
‎06-27-2019 05:05 PM
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