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Design Example - Stratix IV RLDRAM II UniPHY 533MHz x36

Design Example - Stratix IV RLDRAM II UniPHY 533MHz x36

Last Major Update

Initial Release – Jan 2011 – Stratix IV RLDRAM II x36 533 MHz, Quartus II v11.1, RLDRAM II Controller with UniPHY. 


Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a RLDRAM II interface working with a Stratix III FPGA using a single component on the Stratix III internal memory board. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the UniPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process. Volume 6 of the External Memory Interface Handbook should be used for a more thorough walkthrough.

The lab creates a 36bit 400MHz RLDRAM II external memory PHY and controller using Altera’s RLDRAM II Controller with UniPHY IP. The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the RLDRAM II functionality


Design Specifications

The table below lists the specifications for this design:

Quartus versionQuartusII v11.1
KitStratix IV development board
Memory deviceRLDRAM II (Micron MT49H16M36HT-18)
Memory speed533MHz
Memory topologysingle component, x36
IP usedRLDRAM II Controller with UniPHY and generated example top Quartus project


Lab Steps

The lab uses Quartus II v11.1 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features. 

Three files have been pre-designed for this lab to save time.

  • A pin location assignments tcl script
  • A signal tap file for debug of the interface design that has been created
  • A board trace models for SIII & MT49H16M36HT-18 Board tcl script

A Quartus archive for the final project is also included for reference. 

Files for this lab are located in this zip file –

Create a new folder for the project and place the files in it 


Design Generation


1. Use the Megawizard Plug-in Manager to generate a RLDRAM II Controller with UniPHY

  • Start Quartus, open MegaWizard Plug-In Manager and create a new variation
  • In the Megawizard GUI, set device family to be Stratix IV
  • The IP is located under the folders Interfaces/External Memory/RLDRAM II, choose RLDRAM II Controller with UniPHY
  • If your license for ModelSim can not support multiple HDL languages then chose verilog as output file type
  • For the name of the output file, browse to the folder you created above, give the instance the name “rldram”, click Open, click Next to open the IP GUI


2. Set parameters for Memory Controller with UniPHY

On the right of the GUI are some Memory Presets, click Micron MT49H16M36HT-18 and apply

  • General Settings Tab

        - Set Speed Grade to 2 

        - Set Memory Clock Frequency to 533MHz 

        - Set PLL Reference Clock Frequency to 50MHz 

        - For Full or half rate on Avalon-MM interface, select Half. This option allows you to choose between the full-rate and half-rate controller, and define the bus data width between the controller and the PHY.

        - For Additional Address/Command clock phase, select 0.

  • Advanced Settings

       - Select 4 for maximum Avalon-MM burst length

       - Select 1.8V HSTL for I/O standard

       - Turn on Master for PLL/DLL sharing to instantiate its own PLL. If the Master for PLL/DLL sharing option is disabled, the PLL clock shares with other identical UniPHY core.

      -Under Example Testbench Simulation Options, turn on Skip memory initialization to reduce simulation time.

  •  Controller Settings Tab – Select 0 for Controller Latency
  •  Memory Parameters Tab

       - Select tRC=8, tRL=8, tWL=9, f=533–175MHz for Memory Mode Register Configuration

      - Keep the rest of this page to default

  • Memory Timing Tab - Again loaded from the preset, users should confirm data is correct against the memory vendor datasheet
  •  Board Settings Tab - Users should do board simulation for proper values in this page

       - In the Board Settings tab, set the Setup and Hold Derating parameters to the specified values below:

               tAS Vref to CK/CK# Crossing: 0ps

               tAS VIH MIN to CK/CK# Crossing: -100ps 

               tAH CK/CK# Crossing to Vref: 0ps

               tAH CK/CK# Crossing to VIH MIN: -50ps 

               tDS Vref to CK/CK# Crossing: 5ps

               tDS VIH MIN to CK/CK# Crossing: -100ps 

               tDH CK/CK# Crossing to Vref: 3ps

               tDH CK/CK# Crossing to VIH MIN: -50ps

         - Set INI parameters to 0ps for single chip select.

         - Set the Board Skews parameters to the specified values below:

              Maximum CK delay to device: 390ps

               Maximum DK delay to device: 288ps

              Minimum delay difference between CK and DK: 21ps 

              Maximum delay difference between CK and DK: 23ps 

              Maximum delay difference between devices: 0ps 

              Maximum skew within DK group: 70ps

              Maximum skew between DK groups: 7ps 

              Average delay difference between Address/Command and CK: 12ps 

              Average delay difference between Data and DK: 12ps

              Average delay difference between Data and QK: 0ps 

              Maximum skew within Address/Command bus: 13ps

  • Click “Finish” to start IP generation. Check important messages during generation. After IP is successfully generated, click Exit to close GUI

3. Open the example project generated by the Megawizard 

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their UniPHY IP configuration on hardware.

  • Open the example project located in <variation_name>_example_design/example_project. If the device you are using does not match the device in the example project, change the device in the project. 

4. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step

5. Assign the pin and DQ group settings 

Run the tcl script rldram_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard 

  • Verify in the Assignment Editor that pin assignments have been created successfully

6. Assign the pin locations for external memory systems.

  • Run the S4_Host_RLDRAM_PinLocations.tcl script to assign pin locations for the targeted kit
  • Verify in Pin Planner or Assignment Editor that pin locations have been created successfully


7. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.

8. Perform RTL Simulation(optional)

Design Analysis

 1. Timing Analysis results

  •  In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

      - Check the summary at the bottom of that report 

      - Check that all set up and hold timings pass 

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design. 


 2. On board debug with Signal Tap 

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation

  • Program the kit FPGA with the .sof
  • Run Signal Tap Analysis

       - Restart the driver

       - Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high. 

       - Also check that calibration was successful and that the PLL is locked 



Design Simulation


The Quartus II software creates a complete design example for functional simulation in the <variation_name>_example_design/simulation/ directory. To run the RTL simulation, perform the following steps: 

• Open the generated example project for the design example simulation, <variation_name>_example_design/simulation/<variation_name>_ example_sim.qpf. 

• Select Tools -> Tcl Scripts... -> generate_sim_verilog_example_design.tcl and click "Run". 

• Open Modelsim. 

• Move into the directory ./verilog/mentor or ./vhdl/mentor.

• Start Modelsim and run the "" script: in Modelsim, enter "do".

• The simulation will stop once the test complete signal goes high in the test bench 

• CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset 

• Observe the results in the ModelSim Wave window




Update History

1. Initial Release - May 18h 2011 - SIV RLDRAM II x36 533MHz, QuartusII v11.0, UniPHY, SIV E FPGA development board.

See Also

1. List of designs using Altera External Memory IP 


 External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

 Key Words

UniPHY, RLDRAM II, Design Example, External Memory 

© 2011 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

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Last update:
‎06-25-2019 06:07 PM
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