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Design Example : Stratix V DDR3 SDRAM UniPHY 666MHz Quarter Rate

Design Example : Stratix V DDR3 SDRAM UniPHY 666MHz Quarter Rate


Last Major Update

Initial Release – June 2012 – Stratix V DDR3 SDRAM UniPHY 666MHz Quarter Rate, Quartus II v12.0, DDR3 SDRAM Controller with UniPHY.


Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to design a 64-bit wide, 666-MHz DDR3 SDRAM interface working with a Stratix V FPGA using a 64-bit wide DDR3 SDRAM interface comprises four MT41J128M16HA DDR3 SDRAM components. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the UniPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process. 

 

The UniPHY IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 SDRAM functionality.

 

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
Quartus versionQuartusII v12.0
FPGA5SGXEA7K2F40C2ES
KitDevelopement Kit
Memory deviceDDR3 SDRAM (Micron MT41J128M16HA)
Memory speed800MHz
Memory topologyx72-bit, 4 DDR3 SDRAM components 
IP usedDDR3 SDRAM Controller II with UniPHY IP and generated example top Quartus project

 

Lab Steps

The lab uses Quartus II v12.0 and has Modelsim set up for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

 

A Quartus archive for the final project is also included for reference.

Files for this lab are located in this zip file - Uniphy_ddr3_quarter_rate.zip.

Create a new folder for the project and place the files in it.


Design Generation 

1. Use the Megawizard Plug-in Manager to generate a DDR3 SDRAM Controller with UniPHY

Start Quartus, open MegaWizard Plug-In Manager and create a new variation 

• In the Megawizard GUI, set device family to be Stratix IV 

• The IP is located under the folders Interfaces/External Memory/DDR3 SDRAM, choose DDR3 SDRAM High Performance Controller with UniPHY v12.0

• If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type 

• For the name of the output file, browse to the folder you created above, give the instance the name “ddr3”, click Open, click Next to open the IP GUI 


2. Set parameters for Memory Controller with UniHY

• PHY Settings Tab

1. Set Speed grade to 2.

2. Set Memory clock frequency to 666 MHz

3. Set PLL reference clock frequency to 100 MHz.

4. Select Quarter for quarter-rate Avalon-MM interface.

5. Select Skip calibration for Auto-calibration mode under Example Testbench Simulation Options.

 

• Memory Parameters Tab

1. Select Discrete Device for Memory format.

2. Select 800 MHz for Memory device speed grade.

3. Type 72 for Total interface width.

4. Select 1 for Number of slots and Number of chip select per slot, select 1.

5. Select 1 for Number of clocks per chip select.

6. Type 14 for Row address width.

7. Type 10 for Column address width.

8. Type 3 for Bank address width.

9. Select 11 for Memory CAS latency setting under Memory Initialization Options, 

10. Select RZQ/6 for Output drive strength setting.

11. Select 6 for Memory write CAS latency setting.

12. Select RZQ/4 for Dynamic ODT(Rtt_WR) setting. 


• Memory Parameters Tab

1. Set tIS (base) to 170ps

2. Set tIH (base) to 120ps

3. Set tDS(base) to 10ps

4. Set tDH(base) to 45ps

5. Set tDQSQ to 100ps

6. Set tDQSS to 0.27 cycles

7. Set tDSH to 0.18 cycles

8. Set tDSS to 0.18 cycles

9. Set tRAS to 35.0ns

10. Set tRCD to 13.75ns

11. Set tRP to 13.75ns

12. Set tRFC to 110ns

13. Set tWTR to 4 cycles

14. Set tFAW to 30.0ns

15. Set tRRD to 6.0ns


• Board Settings Tab 

1. Users should do board simulation for proper values in this page:

     - In the Setup and Hold Derating option, select 'Specify slew rates to claculate setup and hold times', and set the slew rate parameters to the specified values below:

         CK/CK# slew rate (Differential): 4.348V/ps

         Address and command slew rate: 2.174V/ns 

         DQS/DQS# slew rate (Differential): 4.348V/ns

         DQ slew rate: 2.174V/ns 


      - Set the Board Skews parameters to the below value:

         Maximum CK delay to DIMM/device : 0.6ns

         Maximum CK delay to DIMM/device : 0.6ns

         Minimum delay difference between CK and DQS : -0.01ns

         Maximum delay difference between CK and DQS : 0.01ns

         Minimum skew within DQS group : 0.02ns

         Minimum skew between DQS group : 0.02ns

         Average delay difference between DQ and DQS : 0.0ns

         Maximum skew within address and command bus: 0.02ns

         Average delay difference between address and command and CK: 0.0ns


    - Select the option 'DQ/DQS Package Deskew' and 'Address/Command Package Deskew' under Board Skews parameters.


• Controller Settings Tab 

1. Set 64 for Maximum Avalon-MM burst length under Avalon Interface


3. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their UniPHY IP configuration on hardware. 

• Open the example project located in <variation_name>_example_design/example_project. If the device you are using does not match the device in the example project, change the device in the project. 


4. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step.


5. Assign the pin and DQ group settings 

Run the tcl script <variation_name>_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard 

• Verify in the Assignment Editor that pin assignments have been created successfully 


6. Assign the pin locations

Pin locations for external memory systems are not automatically created. 

• Run the SV_ddr3_pin_locations.tcl script to assign pin locations for the targeted kit 

• Verify in Pin Planner or Assignment Editor that pin locations have been created successfully


7. Do a Full Compile'

This should take about 10 minutes depending on the compiling PC.



Design Analysis 

'1. Timing Analysis results 

'• In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

- Check the summary at the bottom of that report

- Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.

2. On board debug with Signal Tap 

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation 

• Program the kit FPGA with the .sof 

• Run Signal Tap Analysis

- Restart the driver

- Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.

- Also check that calibration was successful and that the PLL is locked



Design Simulation 

The Quartus II software creates a complete design example for functional simulation in the <variation_name>_example_design/simulation/ directory. To run the RTL simulation, perform the following steps:

• Open the generated example project for the design example simulation, <variation_name>_example_design/simulation/<variation_name>_ example_sim.qpf. 

• Select Tools -> Tcl Scripts... -> generate_sim_verilog_example_design.tcl and click "Run". 

• Open Modelsim. 

• Move into the directory ./verilog/mentor or ./vhdl/mentor.

• Start Modelsim and run the "run.do" script: in Modelsim, enter "do run.do".

• The simulation will stop once the test complete signal goes high in the test bench 

• CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset 

• Observe the results in the ModelSim Wave window 


 

Notes/Comments

This design example looks invalid. The memory timing has not been changed to the lower speed being run at. The CL=11 and CWL=6 are not supported by Micron for the 800Mhz DDR3 being used.


Update History

Initial Release – June 2012 – Stratix V DDR3 SDRAM UniPHY 666MHz Quarter Rate, Quartus II v12.0, DDR3 SDRAM Controller with UniPHY. 

 

See Also

1. List of designs using Altera External Memory IP 


External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

 

Key Words

UniPHY, DDR3 SDRAM, Design Example, External Memory , Stratix V, SV

Version history
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Last update:
‎06-27-2019 05:08 PM
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