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Design Example: Stratix V QDR II SRAM UniPHY 550 MHz x18 using external PLL

Design Example: Stratix V QDR II SRAM UniPHY 550 MHz x18 using external PLL



Last Major Update

Initial Release – August 2012 – Stratix V QDR II+ SRAM x18 550 MHz, Quartus II v12.0, QDR II+ SRAM Controller with UniPHY.


Design Overview 

This design is meant as a demo style lab. It very briefly covers the steps required to design a 18-bit wide, 550-MHz QDR II+ SRAM interface working with a Stratix V FPGA using a 18-bit wide 32-Mb Cypress CY7C2263KV18-550BZXI 550-MHz QDR II+ SRAM.The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA when using an external PLL to interface with the slave configured UniPHY IP as shown in figure below.


4/45/Top_level.jpg ( Top level.jpg - click here to view image )

Design Specifications 

The table below lists the specifications for this design: 

 

c/ca/Table.jpg ( Table.jpg click here to view image )

Lab Steps

The lab uses Quartus II v12.0 and assumes the reader is a competent user of these tools and many of their features. 

Four files have been pre-designed for this lab to save time.

  • A pin location assignments tcl script (pin_location.tcl)
  • A signal tap file for debug of the interface design that has been created (stp1.stp)
  • A virtual pins assignments script for this design (virtual_pin.tcl)
  • A RTL file consisting of ALTERA_PLL and PHYCLK buffer (user_pll.v)

A Quartus archive for the final project is also included for reference. Files for this lab are located in this zip file -  emi_qdrii_plus_stratixv

Create a new folder for the project and place the files in it.


Design Generation

1. Create a new project in Quartus 

a. In the Directory, Name, Top-Level Entity GUI, enter your working directory. Enter the name of project as sv_qdrii.

b. In the Family & Device Settings GUI, select 5SGXEA7K2F40C2ES from the Available devices list

c. ClickFinish.


2. Use the Megawizard Plug-in Manager to generate a QDR II+ SRAM Controller with UniPHY 

Start Quartus, open MegaWizard Plug-In Manager and create a new variation 

• In the Megawizard GUI, set device family to be Stratix V 

• The IP is located under the folders Interfaces/External Memory/QDR II and QDR II+ SRAM, choose QDR II+ SRAM High Performance Controller with UniPHY v12.0 

• If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type 

• For the name of the output file, browse to the folder you created above, give the instance the name “qdrii”, click Open, click Next to open the IP GUI 


3. Set parameters for Memory Controller with UniPHY 

a. Set the parameter values for QDR II+ SRAM Controller with UniPHY as shown in table below: 

 6/64/UniPHY.jpg ( UniPHY.jpg - click here to view image )

b Click Finish to generate your MegaCore function variation. The MegaWizard Plug-In Manager generates the following two example design projects. 

• Project for synthesis flow; obtain this file from the <variation_name>_example_design/example_project directory. 

• Project for simulation flow; obtain this file from the <variation_name>_example_design/simulation directory. 

Each project includes full design RTL and the Quartus II project files (.qpf and .qsf) that you can use with minimal modifications. 


4. Use the Megawizard Plug-in Manager to generate Altera PLL 

Open MegaWizard Plug-In Manager and create a new variation 

• In the Megawizard GUI, set device family to be Stratix V 

• The IP is located under the foldersI/O, choose Altera PLL v12.0

For the name of the output file, browse to the folder you created above, give the instance the name “pll”, click Open, click Next to open the IP GUI


5. Set parameters for Altera PLL

a. Set the parameter values for Altera PLL as shown in table below. You need to create and compile a UniPHY design with no PLL sharing to get the output clocks settings from PLL usage summary from Fitter report 

f/f1/PLL.jpg ( PLL.jpg - click here to view )

 b Click Finish to generate your MegaCore function variation.


6. Set Top-Level Entity File

a. Open the qdrii_example .v located under qdrii_example_design\example_project\ qdrii_example directory.


b. Copy this file to your selected working directory and rename as qdrii_example_top_level.v. Open qdrii_example_top_level.v and perform the steps below:

i. Rename the module as qdrii_example_top_level.

ii. Comment out all the instantiation/modules which are related to qdrii_example_if1. When you select Slave mode for PLL sharing in UniPHY GUI, the example design is generated for this UniPHY and the PLL is instantiated within another UniPHY master variant, which is named as qdrii_example_if1.

iii. Make proper connection to connect PLL, PHYCLK buffer to UniPHY. PHYCLK buffer is based on WYSIWYG flow and refer to <variation_name> _example_if1_pll0.sv file for this module instantiation. Refer to the pre-designeduser_pll.v for the connection between PLL and PHYCLK buffer.

iv. Assign afi_reset_n as AND output from pll_locked, global_reset_n and soft_reset_n.


c. Set qdrii_example_top_level.v as Top-Level Entity.


d. Add the following files to your project:

i. pll.qip

ii. qdrii_example.qip (you need to comment out the assignments related to qdrii_example_if1)


7.Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step.


8. Assign the pin and DQ group settings 

i. Run the tcl script qdrii_example_if0_p0_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard. Verify in the Assignment Editor that pin assignments have been created successfully. 

ii. Modified unrecognized global signal assignments made to PLL output clocks to target correct PLL instance.


9. Assign the pin locations

Pin locations for external memory systems are not automatically created.

  • Run the pin_location.tcl script to assign pin locations for the targeted kit
  • Run thevirtual_pin.tcl script to assign virtual pins
  • Verify in Pin Planner or Assignment Editor that pin locations have been created successfully


10. Create the SignalTap II Logic Analyzer Files to Project

To verify Memory IP functionality, please use the SignalTap II Logic Analyzer. To add the SignalTap II logic analyzer, follow the steps indicated under Verifying Memory IP Using the SignalTap II Logic Analyzer section in Altera External Memory Interfaces Handbook, Chapter 11: Debugging Memory IP.


11. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.

 

Design Analysis

1. Timing Analysis results 

• In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder 

- Check the summary at the bottom of that report 

- Check that all set up and hold timings pass 

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.


2. On board debug with Signal Tap 

Open the Signal Tap file and program the generated .sof file. 

Run Analysis and ensure that test complete goes high (signal tap is trigger on this)as it indicates the end of the driver testing stage 

Ensure the calibration and driver test was successful and that the PLL is locked 


Design Simulation

This section describes RTL (functional) simulation. After you have generated your design, the Quartus II software creates a complete design example for functional simulation in the <variation_name>_example_design/simulation/ directory. This design example includes the driver, testbench, and the memory model that allows you to perform functional simulation on the design.The simulation example design is available for both Verilog and VHDL.Use the ModelSim-Altera simulator to perform the functional simulation.


To run the RTL simulation, perform the following steps:

1. Open the generated example project for the design example simulation,<variation_name>_example_design/simulation generate_sim_example_design.qpf.


2. Change the device in the design example to the actual device you are targeting for your design.


3. To generate the Verilog example design, selectTools -> Tcl Scripts... -> generate_sim_verilog_example_design.tcl and click "Run".

  • Alternatively, you can run "quartus_sh -t generate_sim_verilog_example_design.tcl" at Tcl console. The generated files will be found in the subdirectory "verilog". To generate the VHDL example design, select Tools -> Tcl Scripts... -> generate_sim_vhdl_example_design.tcl and click "Run".Alternatively, you can run "quartus_sh -t generate_sim_vhdl_example_design.tcl" at Tcl console. The generated files will be found in the subdirectory "vhdl".


4. Open the following two files and modified them to match with the changes that you had made in synthesis top-level:

a.qdrii_example_sim.v located under \verilog directory

b. qdrii_example_sim_e0.v located under \verilog\submodules directory


5. To get a simulation with external PLL interface with UniPHY, include the PLL design files and PLL simulation model file (pll.vo) in msim_setup.tcl under verilog/mentor directory.


6. When using UniPHY, the PLL outputs clock phase shift may differ for both synthesis and simulation. To get the correct PLL output clocks phase shift, refer to *_PHASE_SIM parameters in *_pll0.sv which is generated when the UniPHY is configured as master for PLL Sharing .


7. Open the PLL simulation model files (pll.vo) and modified the PLL output phase shift to align with that of in *_pll0.sv file.


8. To simulate the example design using Modelsim AE/SE:

• Start Modelsim.

• Change directory to <variation_name>_example_design/simulation/verilog/mentor. Alternatively, change the directory to<variation_name>_example_design/simulation/vhdl/mentor if you generate VHDL example design

• In transcript window, type "do run.do" to run the run.do file.The simulation will stop once the test complete signal goes high in the test bench.CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset.Observe the results in the ModelSim Wave window

 

Notes/Comments

For a list of supported and unsupported features in the QDR II and QDR II+ SRAM Controller with UniPHY, refer to the QDR II and QDR II+ SRAM Controller with UniPHY User Guide. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

 

Update History

Initial Release – August 2012 – Stratix V QDR II+ SRAM x18 550 MHz, Quartus II v12.0, QDR II+ SRAM Controller with UniPHY.

See Also 

1. List of designs using Altera External Memory IP

 

External Links 

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 


Key Words

UniPHY, QDR II+ SRAM, Design Example, External Memory , Stratix V, SV , Altera PLL, PLL Slav

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Last update:
‎06-25-2019 11:14 PM
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