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Design Example - XAUI

Design Example - XAUI



Contents

 [hide

External Links

intel FPGA Transceiver PHY IP Core User Guide (PDF) 

Altera Stratix V Device Documentation

Altera Avalon Memory-Mapped Interface Specification (PDF)


Design File

for QuartusII v11.0 

Altera XAUI Design File for v11.0(ZIP)  

for QuartusII v13.1 

Altera XAUI Design File for v13.1(ZIP)  

Design Specifications

The table below lists the specifications for this design:  

AttributeSpecification
Device FamilyStratix V GX
FPGA5SGXMA7K2F40C2
Quartus versionQuartusII v11.0, b157
Modelsim versionModelsim SE v6.6d
Datarate3.125Gbps
Data patternPRBS 7
Number of channels4
IP usedXAUI PHY IP, Traceiver Reconfiguration Controller

  

The table below lists the specifications for the design: &nbsp for QuartusII v13.1 b162;

AttributeSpecification
Device FamilyStratix V GX
FPGA5SGXMA7K2F40C2
Quartus versionQuartusII v13.1, b162
Modelsim versionModelsim SE v10.0d
Datarate3.125Gbps
Data patternPRBS 7
Number of channels4
IP usedXAUI PHY IP, Traceiver Reconfiguration Controller

 

Design Overview

This design implements the following blocks:

  1. XAUI PHY IP
  2. Transceiver Reconfiguration Controller
  3. PRBS Generator
  4. PRBS Checker
  5. Avalon Memory-Mapped (MM) Master







Compilation in Quartus 

1) Download and unzip the zip files linked above into a folder to be used as the download directory.


2) Open the project file (.qpf) by going to File > Open Project and navigating to <download_directory>\SV_XAUI\source. Open SV_XAUI.qpf. 


3) Use the Megawizard Plug-in Manager to generate Altera Generated IP Before compiling you must regenerate the Altera generated IP using the Megawizard. You will perform this step twice - once for the top_xaui.v and once for the top_reconfig.v. Open MegaWizard Plug-In Manager and choose edit a variation. 

  • Select the IP you want to edit and generate (The .v file will be located in your project directory).
  • If your license for ModelSim can not support multiple HDL languages then chose verilog as output file type (The default settings will work for this example). 
  • Select the options for the IP you want to generate (The default settings will work for this example), and click Finish. 

After the previous steps have been completed, you can compile the entire design by going to Processing > Start > Start Analysis and Synthesis. 

4) During compilation you can expect following critical warnings

  • Critical Warning (169085): No exact pin location assignment(s) for 183 pins of 183 total pins.
  • Critical Warning: Timing requirements not met.

Simulation Guidelines

The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl


  1. Initial Release - May 05 2011 


 See Also

  1.  Transceiver design examples 

 

Key Words

Stratix V, XAUI PHY IP, Tranceiver Reconfiguration Controller 


   

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Version history
Revision #:
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Last update:
‎06-25-2019 06:09 PM
Updated by:
 
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