1. In the "Library" tab, select you "AXI3 Slave Component" and click the "Add.." button.
2. In the dialog box, note that the component parameters appear.
3. Change "AXI_ID_W" to 12.
The SoC HPS AXI bridge masters forward a 12-bit ID, the slaves must be configured to accept a minimum or 12 ID bits.
4. Ensure that the "AXI_DATA_W" parameter is set to 64 and the "AXI_ADDRESS_W" parameter is set to 12.
5. Click "Finish"
6. Scroll to the bottom of the "System Contents" tab to see your "AXI3 Slave Example" component instantiated in the syste.
7. Connect the "AXI3 Slave Example" component's Clock Input, Reset Input, and AXI Slave to clk_0.clk, clk_0.clk_reset, and hps_0.h2f_axi_master respectively.
Instantiating an AXI Default Slave
The AXI Specification requires that the interconnect respond to all transactions, even if the address space is not decoded to a slave. In order to comply with this requirement, we will instantiate an AXI Default Slave peripheral which will respond with a DECERR response should the HPS to FPGA AXI Master attempt to access an address which is not decoded to an instantiated component.
1. In the search field of the "Library" tab, type "default" as shown below.
2. Select the "AXI Default Slave" component and click "Add...".
2. In the "AXI Default Slave" dialog box, set the AXI master ID width to 12 and the AXI data width to 64
3. Click "Finish"
5. Connect the "AXI Default Slave" component's Clock Input, Reset Input, and AXI Slave to clk_0.clk, clk_0.clk_reset, and hps_0.h2f_axi_master respectively.
5. In the "System Contents" tab, right click on the column headers and check "Show Default Slave Column".
6. In the "System Contents" tab, scroll to the right until the "Default Slave" column is visible.
7. Check the "Default Slave" column box for the "AXI Default Slave".
Note that the base address for the AXI Default Slave changes to default.
Generating the QSys System and Compiling in Quartus
1. Click the QSys "Generate" menu then select "Generate.."
2. Ensure that under the Synthesis section, "Create HDL Design Files for synthesis:" is set to "Verilog"
3. Click the "Generate" button, then click "Save".
4. After the QSys generation is complete, click "Close" in the "Generate" dialog box and return to the Quartus GUI.
Four warnings will be generated. These warnings can be ignored.
5. In the Quartus GUI, go to the "Processing" menu and select "Start Compilation" to compile the project.
Note: as this is not a Quartus or QSys class, all setup necessary for compiling the QSys system has been done.
If you need to learn how to include QSys files in your project and configure the project settings, please attend
one of the classroom or on-line trainings.
6. When the Quartus compile is complete, proceed to the next section of the lab.
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