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DisplayPort Design Example 13.1 (TX-RX)

DisplayPort Design Example (RX and TX)

 

Downloadable Design Examples

 

Instructions

The zip files include a Quartus project with a hardware demonstration design. The Quartus project has the FPGA configuration file (.sof) and Nios II processor code (.elf) for the demonstration. To run the demontration design, two easy-to-use script files are provided under software directory: rerun.sh and batch_script.sh

 

  • rerun.sh

This script downloads the SOF and ELF files without creating the Nios II application software (.elf). If you have multiple USB programming cables, pass in a cable name as shown in the example below:

e.g: ./rerun.sh USB-Blaster[USB-2] (Note: the cable name 'USB-Blaster[USB-2]' should not include any space)

If you have multiple USB programming cables and are not sure of the cable name, use 'jtagconfig' command in a nios2 terminal to get the correct cable.

If you have only one USB programming cable, then run the script without a cable name.

  • batch_script.sh

This script creates the Nios II application software (.elf), download the SOF and ELF files. If you have multiple USB programming cables, pass in a cable name as shown in the example below:

e.g: ./batch_script.sh USB-Blaster[USB-2] (Note: the cable name 'USB-Blaster[USB-2]' should not include any space)

If you have only one USB programming cable, then run the script without a cable name.

Hardware Requirements

To view the results using the design example, the following hardwares are required.

  • Altera FPGA Development Kit
  • Desktop PC with a GPU supporting DisplayPort and DVI-D outputs
  • DisplayPort Capable Monitor
  • Bitec HSMC Daughter Board
  • Others

- DisplayPort Cables (2)

- DVI-D Cable

- Power Supply for FPGA board

- JTAG Download Cable (USB-Blaster II or USB-Blaster)

Hardware Setup

f/ff/DP_Demo_HW_Setup.JPG ( DP Demo HW Setup.JPG - click here to view image )

 

Reference Documents

Altera DisplayPort MegaCore Function User Guide

Altera Transceiver PHY IP Core User Guide

Altera Video and Image Processing Suite User Guide

Altera Nios II Software Developer's Handbook

Avalon Interface Specifications 

 

Introduction

This design example demonstrates the use of the Altera DisplayPort MegaCore Function in a receive and transmit mode application. The design example is implemented using Altera’s Qsys tool and standalone HDL modules. The design example demonstrates the following:

  • Altera’s DisplayPort (DP) sink and source in real application
  • A video loop-through system based on Altera's DP MegaCore Function
  • Quick starting point for building a video system

 

Figure below is the system diagram of the design example.

6/6b/DP_RX_Demo_System.jpg ( DP RX Demo System.jpg - click here to view image )

This document has the following sections:

  • Functional Description
  • Software Description
  • Using the Design Example
  • Viewing the Results
  • Document Revision History

 

Functional Description

This design example receives video data over the DP RX link. The received video is converted to Avalon-ST image stream and stored into external memory. The buffered image is then mixed with a 1920x1200 background color bar and is sent to the DP source. The combined image is transmitted to a DP capable monitor over DP TX link.

Figure below shows a block level diagram of the design example. 

The design example has the following four major functional components. 

  • System Reset
  • Clocking
  • Link Initialization

- Transceiver Reconfiguration

- DP TX link

- DP RX link

- Link Bandwidth

- DP Configuration Data Fields

  • Qsys System - Video Receive and Transmit Paths

- DP sink and source

- VIP Suite IP Cores

- Nios II Processor

The following sections describe these major functional components.

5/55/DP_RX_Design_Block_Diagram.jpg ( DP RX Design Block Diagram.jpg - click here to view image )

 

System Reset

The system reset in the design example is triggered by an external hard reset (e.g. push-button), the PLLs not achieving lock, or the PLLs losing lock. The system reset signal is kept asserted for 32K clock cycles, after the PLLs have locked to their reference clock. This ensures the system stays in the reset state until the PLL output clocks reach a stable state.

 

Clocks

The design example instantiates two PLLs in the top level module: Transceiver PLL and Video PLL. These PLLs generate internal clocks required by the design. Table 1 lists the clocks used in the design, their frequencies, and the main blocks driven by the clock signals.

Clock Signal Description Loads
clk 100 MHz external clock source
  • DisplayPort IP core Avalon-MM interface
  • Nios II processor and peripherals
  • DisplayPort IP core transceiver reconfiguration and mgmt logic
  • Video PLL input clock
162 MHz Transceiver PLL outclk0. Used as the transceiver reference clock for 1.62 Gbps rate
  • DisplayPort transceiver PHY reference Clock
270 MHz Transceiver PLL outclk1. Used as the transceiver reference clock for 2.7, and 5.4 Gbps rates
  • DisplayPort transceiver PHY reference Clock
154 MHz Video PLL outclk0. Video clock for Avalon Streaming (Avalon-ST) video data path for 1920x1200 @ 60 Hz
  • Main video data path clock for DisplayPort IP core video input and output, and VIP suite IP cores
16 MHz Video PLL outclk1. Clock for 1 Mbps AUX channel interface
  • DisplayPort IP core TX and RX AUX channel controller
  • TX and RX AUX channel debug FIFOs
ddr_clk 100 MHz external clock source for memory controller
  • DDR3 SDRAM controller IP core for Frame Buffer

 

Link Initialization

Transceiver Reconfiguration

During link training, the following transceiver features are reconfigured through the transceiver reconfiguration controller IP core and a finite state machine (FSM) to obtain a functional link. 

  • Data rate
  • Output voltage swing (Vod)
  • Pre-emphasis

 

Figure below is the diagram of the reconfiguration logic block, DP source and sink, and the Nios II processor in the design example.  

8/84/DP_XCVR_Reconfiguration_Control.jpg ( DP XCVR Reconfiguration Control.jpg - click here to view image )

 

Table below lists the custom RTL modules responsible for the transceiver data rate and analog reconfiguration during link training. The RTL modules are available in clear text Verilog in the design example. 

Module Name Description
reconfig_mgmt_hw_ctrl.v This module is a high level FSM responsible for generating the control signals to reconfigure the VOD, pre-emphasis and selects PLL reference clock, and reconfigures clock divider setting. It loops through all the channels and transceiver settings.
reconfig_mgmt_write.v This module is instantiated in reconfig_mgmt_hw_ctrl.v and responsible for generating a reconfiguration write cycle on the Avalon-MM interface to the transceiver reconfiguration controller IP core. This is done with a simple state machine that steps through the low level commands to write to the transceiver reconfiguration controller IP.
dp_mif_mappings.v This module is instantiated in reconfig_mgmt_hw_ctrl.v. It maps the 2-bit requested data rates to the Memory Initialization File (MIF) settings that need to be written during a direct reconfiguration mode of the transceiver reconfiguration controller IP core.
dp_analog_mappings.v This module is instantiated in reconfig_mgmt_hw_ctrl.v and maps per-channel 2-bit VOD and 2-bit pre-empahsis settings from the DP source to the transceiver analog settings. To enable analog reconfiguration, turn on Support analog reconfiguration in the DP source parameter editor. By default, the DP source analog reconfiguration is disabled. If you are not using an external re-driver solution, this should be enabled.

The DP main link in the design example uses external re-driver devices on the Bitec HSMC daughter card. Therefore, the DP source analog reconfiguration feature is not enabled. The re-driver’s output is automatically adjusted based on link training result. The input equalization (EQ) settings are programmable through the I2C interface. The ‘main.c’ in the design example software has the example code that allows you to configure the re-driver EQ settings. Depending on the channel conditions such as the cable quality and length, you may need to adjust these settings.

 

DP TX Link

The DP source link must be initialized through link training before transporting a main video stream. The training sequence is initiated by the link policy maker running on the Nios II processor after detecting a Hot Plug Detect (HPD) event asserted by a sink device.

 

DP RX Link

The DP sink implements a finite state machine (FSM) that decodes the incoming AUX channel transaction requests. All lane training and EDID link layer services are performed by the AUX channel FSM in non-GPU mode, enabling DP sink to run autonomously without a controller.

DP sink instantiations greatly benefit from and may optionally use an embedded controller (Nios II processor or another controller). If your design needs a controller to control DP sink instances, turn on Enable GPU control in the DP sink parameter editor.

 

Qsys System - Video Path

The video receive and transmit function is implemented using Altera’s Qsys tool. Figure below is the block diagram of the Qsys system showing the video receive and transmit paths that include the DP source, DP sink, VIP Suite IP cores, and SDRAM controller. 

b/ba/DP_RX_Video_Path.jpg ( DP RX Video Path.jpg - click here to view image )

 

DisplayPort Sink and Source

Altera's DisplayPort MegaCore function has the following features: 

  • 1, 2, or 4 lane operation
  • 1.62, 2.7, and 5.4 Gbps rate per lane
  • 16, 18, 20, 24, 30, 32, 36, or 48 bits per pixel (bpp) color depths
  • RGB and YCrCb color modes
  • Source

- Embedded controller AUX channel operation

- Accepts standard H-sync and V-sync RGB and YCrCb input video formats

  • Sink

- Finite state machine (FSM), or controller AUX channel operation

- Produces a proprietary video output

  • Support for OpenCore Plus evaluation

- Allows you to evaluate the DisplayPort sink and source in simulation and in hardware before you purchase a license.

 

Figure below is the DP sink parameter editor. 

e/ec/DP_Sink_Parameter_Editor.jpg ( DP Sink Parameter Editor.jpg - click here to view image )

Figure below is the DP source parameter editor. 

8/81/DP_Source_Parameter_Editor.jpg ( DP Source Parameter Editor.jpg - click here to view image )

 

VIP Suite IP Cores

Listed below are the VIP Suite IP cores used for the video paths in the design example.

  • Clocked Video Input

- Converts the clocked video output from DP Sink to Avalon-ST video stream.

  • Clocked Video Output

- Converts the Avalon-ST video stream back to the clocked video format by inserting horizontal and vertical sync and blanking information.

  • Frame Buffer

- Stores the received video frames into external memory.

  • Mixer

- Mixes the background color bar with the foreground image received from the host PC.

  • Test Pattern Generator

- Generates 1920x1200 background color bars

 

VIP Suite IP cores support for OpenCore Plus evaluation that allows you to evaluate the IP cores in simulation and in hardware before you purchase a license.

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Version history
Revision #:
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Last update:
‎08-20-2020 04:30 PM
Updated by:
 
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