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DisplayPort Design Example 14.0 (RX and TX)

Introduction

This document describes an example design that demonstrates Altera DisplayPort Sink (RX) and Source (TX) functions using a video loop-through system. DisplayPort is a next-generation video interface display technology. The Video Electronics Standards Association (VESA) developed the standard as an open digital communication interface for internal chip-to-chip and external box-to-box digital display connections such as:

  • Interfaces within a PC or monitor
  • Interfaces between a PC and monitor or projector
  • Interfaces between a PC and TV
  • Interfaces between a device (e.g. DVD player) and TV

DisplayPort uses packetized data transmission and embeds the clock signal in the serial data stream. It can transmit audio, video, or both simultaneously. It also includes a bidirectional, half-duplex auxiliary (AUX) channel for link and device management. The DisplayPort sink uses a Hot Plug Detect (HPD) when it announces its presence or requires the attention of the source device. The HPD causes the DisplayPort source to initiate link via AUX channel.

Getting Started

The DisplayPort example design supports the following FPGA development boards and requires using a DisplayPort daughter card.

FPGA Board Daughter Card Type Supported DP Link Rates
Stratix V GX Development Board Bitec HSMC Daughter Card 1.62Gbps, 2.7Gbps, 5.4Gbps
Arria V GX Development Board Bitec HSMC Daughter Card 1.62Gbps, 2.7Gbps, 5.4Gbps
Cyclone V GT Development Board Bitec HSMC Daughter Card 1.62Gbps, 2.7Gbps

The main changes in Quartus 14.0 are:

  • A single transceiver reference clock (135MHz) is used for all link rates
  • The transceiver(s) is separated from DisplayPort IP core. Transceivers are manually instantiated outside of the Qsys system

Functional Description

Overview of the Example Design

Clocks

FPGA development boards have various programmable oscillators. The example design uses the default outputs and doesn’t require any programming.

Table below lists the clock inputs for the example design.

Signal Name Frequency Use
clk 100MHz
  • Nios II Processor, Avalon-MM interface, transceiver reconfiguration management clock
  • Used to synthesize AUX channel controller clock (16MHz) and video processing clock
xcvr_pll_refclk board- dependent
  • Used to synthesize single 135MHz(Stratix V, Arria V) or dual 162MHz and 270MHz(Cyclone V) transceiver reference clock(s)

Note: Using REFCLK pins in the transceiver bank gives the best jitter performance. If the REFCLK pins are to be used, reprogram the oscillator clock output to 135MHz using Clock Control GUI.

ddr_clk 100MHz
  • SDRAM controller IP PLL reference clock

VIP suite Frame Buffer writes input pixels to and read video frames from the external SDRAM

DisplayPort IP Core

The example design uses the following parameter settings for the DisplayPort Source and Sink.

  • Maximum video color depth = 8 bpc
  • Maximum link rate = 5.4Gbps for Stratix V and Arria V, 2.7Gbps for Cyclone V
  • Maximum lane count = 4
  • Symbol mode = Quad for Stratix V and Arria V, Dual for Cyclone V
  • Pixel mode = Single
  • Enable AUX debug stream = Enabled
  • Support CTS test automation = Enabled

Symbol mode affects the transceiver parallel bus width and the DisplayPort IP core clock frequency. DisplayPort IP core is synchronized with transceiver parallel clock output whose frequency is link rate / transceiver parallel bus width. The following table shows possible IP core clock frequencies for 5.4Gbps and 2.7Gbps link rates.

Symbol Mode (Transceiver Parallel Bus Width) Link Rate IP Core Clock
Dual (20-bit) 5.4Gbps 270MHz
Quad (40-bit) 5.4Gbps 135MHz
Dual (20-bit) 2.7Gbps 135MHz
Quad (40-bit) 2.7Gbps 67.5MHz

Pixel mode affects user video clock frequency and video port width of the IP core. The following table shows an example for 1920x1200@60Hz with color depth 8 bpc.

Pixel Mode Video Clock Maximum Color Depth (bpc) Video Port Width (pixel*bpc*3)
Single 154MHz 8 24
Dual 154MHz / 2 = 77MHz 8 48
Quad 154MHz / 4 = 38.5MHz 8 96

Nios II Processor

DisplayPort Source requires a processor such as a Nios II processor to act as link policy maker. Enabling the processor control for DisplayPort Sink is optional.

The Nios II processor performs the following functions in the design:

  • Initializes the IP core components
  • Runs software that acts as DP link policy maker
  • Programs the DP RX redriver EQ settings of Bitec DP daughter card
  • Provides access to the IP core status, debug registers

Push Buttons

The following table lists the push button functions and the corresponding board references in each FPGA board.

Function Cyclone V GT Development Board Reference Arria V GX Starter Board Reference Stratix V GX Development Board Reference Description
Reset S1 S7 S7 Resets the demo design
Display configuration status S3 S5 S5 Displays the current Tx and Rx MSA values and link configuration in the Nios II terminal

LEDs

The following table lists the LEDs used in the design and the corresponding board references in each FPGA board.

Function Cyclone V GT Development Board Reference Arria V GX Starter Board Reference Stratix V GX Development Board Reference Description (when ON)
RX video lock status D18 D19 D21 Stable MSA values are received 15 times
RX lane count[4:0] status {D10,D11,D15,D16,D17} {D22,D23,D16,D17,D18} {D9,D10,D18,D19,D20} Current RX lane count: 5’b00001=1 lane, 5’b00010=2 lanes, 5’b00100=4 lanes
PLL lock status D9 D21 D8 Video clock, AUX clock, and transceiver reference clock have achieved lock
FPGA reset status D8 D20 D7 FPGA reset is asserted

Video and Image Processing

The Video and Image Processing block is part of the Qsys system in the design. It receives a video image from the DisplayPort IP core (Sink) and outputs a processed video image to the DisplayPort IP core (Source). The following Video and Image Processing (VIP) suite IP cores are used:

  • Clocked Video Input - Converts DP Sink video output to Avalon-ST Video protocol
  • Frame Buffer - Handles mismatch in RX and TX video data rate via triple-buffering
  • Test Pattern Generator – Generates color bar pattern for background image
  • Alpha Blending Mixer – Overlays the buffered image on top of background color bar
  • Clocked Video Output – Converts Avalon-ST Video protocol to DP Source video input format

The figure below shows the video IP connection in the Qsys system.

 

 

TX and RX Transceivers

The transceiver is excluded from the DisplayPort IP core in Quartus 14.0. Separating the transceiver from the DisplayPort IP core enables flexibility for system design and allows the transceiver PHY to be shared with other display interface IP, if needed.

The Quartus IP Catalog provides a transceiver Native PHY library that includes the transceivers configured for DisplayPort application. DisplayPort transceiver Native PHYs in the IP Catalog are based on the maximum link rate and transceiver parallel bus width.

Maximum link rate:

  • HBR2 (5.4Gbps)
  • HBR (2.7Gbps)
  • RBR (1.62Gbps)

Transceiver parallel bus width:

  • Dual Symbol (20-bit wide)
  • Quad Symbol (40-bit wide)

In Quartus 14.0 and later releases, a single reference clock frequency is supported to generate all link rates. The reference clock frequency used in the DisplayPort transceiver Native PHY libraries is 135MHz.

Transceiver Reconfiguration

TX and RX transceivers are reconfigured when DP Source and Sink auto-negotiate the link configuration during link training:

  • TX / RX link rate
  • TX output voltage swing (VOD) and Pre-emphasis level

The following is a list of RTL modules for transceiver reconfiguration. All RTL modules except for the transceiver reconfiguration controller IP are provided in clear-text.

  • <device>_xcvr_reconfig.v – Transceiver reconfiguration controller IP. <device>: sv for Stratix V, av for Arria V, cv for Cyclone V
  • reconfig_mgmt_hw_ctrl.v – Top-level reconfiguration management FSM that handles reconfiguration request from the DisplayPort IP core
  • reconfig_mgmt_write.v – Generates Avalon-MM write cycles to the transceiver reconfiguration controller
  • dp_mif_mappings.v – Maps DP link rate to the transceiver PLL settings
  • dp_analog_mappings.v – Maps DP VOD and Pre-emphasis levels to the transmitter analog settings

DDR3 Memory

The Frame Buffer uses the external SDRAM to triple-buffer video frames and handles mismatch in RX and TX video data rate. It writes to memory to store input pixels and reads from memory to retrieve video frames and output them.

The table below lists the onboard DDR3 memory configuration and interface clock frequency used in the design.

FPGA board Onboard Memory Configuration Memory Clock* Rate on Avalon-MM Interface*
Stratix V GX FPGA Development Board 16M x 72 400MHz Half
Arria V GX FPGA Development Board 8M x 32 333MHz Quarter
Cyclone V GT FPGA Development Board 16M x 64 300MHz Half

*Qsys SDRAM controller IP setting

For the maximum theoretical bandwidth of the external memory interface, refer to the FPGA board reference manual.

Demo Walkthrough

Setting up and running the DisplayPort hardware demonstration consists of the following steps:

1. Set up the hardware
2. Download the Quartus design project (zip file) from Altera Wiki. The zip file includes all hardware and software files.
3. Open the Nios II Command Shell and run ‘jtagconfig’ to check the JTAG chain
4. Program the FPGA with the SOF and ELF files. To automate this step, the following command scripts are provided in the project’s ‘software’ sub-directory.

rerun.sh - downloads the SOF and ELF files without building application software, and opens the Nios II terminal. To run the script in the Nios II Command Shell:
> source rerun.sh
batch_script.sh – builds the application software, downloads the SOF and ELF files, and open the Nios II terminal. To run the script in the Nios II Command Shell:
> source batch_script.sh

5. View the results

Hardware Setup

The following figure shows Stratix V FPGA Development Board connected to the Bitec daughter card. Plug DP cables to connect the Bitec card TX to the monitor and RX to the PC graphics card.

View the Results

Nios II Terminal

When the command script completes downloading the SOF and ELF files, the Nios II terminal is invoked and displays the link training AUX traffic as shown below.

 

Verify Link Training Result

The Nios II terminal screenshot below shows the Sink side link training is completed successfully and, as a result, the Sink DPCD registers return the following data on read:

  • LANE_ALIGN__STATUS_UPDATED = 0x81
  • LANE0_1_STATUS = 0x77 (2 lanes are locked)
 

The Nios II terminal screenshot below shows the Source side link training is successfully completed and, as a result, the Sink DPCD registers return the following data on read:

  • LANE0_1_STATUS = 0x77 0x77 (the 2nd 0x77 is for LANE2_3_STATUS. 4 lanes are locked)

 

Check MSA Values and Link Configuration

Upon successful link training on both Source and Sink sides, the PC desktop image is received and looped out to the DisplayPort monitor. You can check the following by pressing a pushbutton

 

Desktop Image on Background Color Bar

Upon successful link training on both Source and Sink side, the monitor displays the PC desktop image overlaid on top of background color bars as shown below.

References

DisplayPort IP Core User Guide

VIP Suite IP User Guide

Stratix V GX FPGA Development Kit

Arria V GX FPGA Development Kit

Cyclone V GT FPGA Development Kit

Bitec Displayport Daughter Card with HSMC connector

Download Designs

Quartus 14.0 DisplayPort Hardware Demonstration Design Example for Stratix V GX FPGA Development Kit

Quartus 14.0 DisplayPort Hardware Demonstration Design Example for Arria V GX FPGA Starter Kit

Quartus 14.0 DisplayPort Hardware Demonstration Design Example for Cyclone V GT FPGA Development Kit

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Last update:
‎08-20-2020 09:36 AM
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