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DisplayPort Design Example 14.0 (TX-Only)

DisplayPort Design Example 14.0 (TX-Only)


Introduction

This document describes an example design that demonstrates Altera DisplayPort Source (TX) functions using a video loop-through system. DisplayPort is a next-generation video interface display technology. The Video Electronics Standards Association (VESA) developed the standard as an open digital communication interface for internal chip-to-chip and external box-to-box digital display connections such as:

  • Interfaces within a PC or monitor
  • Interfaces between a PC and monitor or projector
  • Interfaces between a PC and TV
  • Interfaces between a device (e.g. DVD player) and TV

DisplayPort uses packetized data transmission and embeds the clock signal in the serial data stream. It can transmit audio, video, or both simultaneously. It also includes a bidirectional, half-duplex auxiliary (AUX) channel for link and device management. The Hot Plug Detect (HPD) causes the DisplayPort source to initiate link via AUX channel.


Getting Started

The DisplayPort example design supports the following FPGA development boards and requires using a DisplayPort daughter card.

FPGA BoardDaughter Card TypeSupported DP Link Rates
Stratix V GX Development BoardBitec HSMC Daughter Card1.62Gbps, 2.7Gbps, 5.4Gbps
Arria V GX Development BoardBitec HSMC Daughter Card1.62Gbps, 2.7Gbps, 5.4Gbps
Cyclone V GT Development BoardBitec HSMC Daughter Card1.62Gbps, 2.7Gbps

The main changes in Quartus 14.0 are:

  • A single transceiver reference clock (135MHz) is used for all link rates
  • The transceiver(s) is separated from DisplayPort IP core. Transceivers are manually instantiated outside of the Qsys system


Functional Description

Overview of the Example Design

2/2e/Tx_system.png ( Tx system.png - click here to view image )


Clocks

FPGA development boards have various programmable oscillators. The example design uses the default outputs and doesn’t require any programming.

Table below lists the clock inputs for the example design.

Signal NameFrequencyUse
clk100MHz
  • Nios II Processor, Avalon-MM interface, transceiver reconfiguration management clock
  • Used to synthesize AUX channel controller clock (16MHz) and video processing clock
xcvr_pll_refclkboard- dependent
  • Used to synthesize single 135MHz(Stratix V, Arria V) or dual 162MHz and 270MHz(Cyclone V) transceiver reference clock(s)

Note: Using REFCLK pins in the transceiver bank gives the best jitter performance. If the REFCLK pins are to be used, reprogram the oscillator clock output to 135MHz using Clock Control GUI.

ddr_clk100MHz
  • SDRAM controller IP PLL reference clock

VIP suite Frame Buffer writes input pixels to and read video frames from the external SDRAM


DisplayPort IP Core

The example design uses the following parameter settings for the DisplayPort Source.

  • Maximum video color depth = 8 bpc
  • Maximum link rate = 5.4Gbps for Stratix V and Arria V, 2.7Gbps for Cyclone V
  • Maximum lane count = 4
  • Symbol mode = Quad for Stratix V and Arria V, Dual for Cyclone V
  • Pixel mode = Single
  • Enable AUX debug stream = Enabled
  • Support CTS test automation = Enabled

Symbol mode affects the transceiver parallel bus width and the DisplayPort IP core clock frequency. DisplayPort IP core is synchronized with transceiver parallel clock output whose frequency is link rate / transceiver parallel bus width. The following table shows possible IP core clock frequencies for 5.4Gbps and 2.7Gbps link rates.

Symbol Mode (Transceiver Parallel Bus Width)Link RateIP Core Clock
Dual (20-bit)5.4Gbps270MHz
Quad (40-bit)5.4Gbps135MHz
Dual (20-bit)2.7Gbps135MHz
Quad (40-bit)2.7Gbps67.5MHz

Pixel mode affects user video clock frequency and video port width of the IP core. The following table shows an example for 1920x1200@60Hz with color depth 8 bpc.

Pixel ModeVideo ClockMaximum Color Depth (bpc)Video Port Width (pixel*bpc*3)
Single154MHz824
Dual154MHz / 2 = 77MHz848
Quad154MHz / 4 = 38.5MHz896


Nios II Processor

DisplayPort Source requires a processor such as a Nios II processor to act as link policy maker. Enabling the processor control for DisplayPort Sink is optional.

The Nios II processor performs the following functions in the design:

  • Initializes the IP core components
  • Runs software that acts as DP link policy maker
  • Programs the DP RX redriver EQ settings of Bitec DP daughter card
  • Provides access to the IP core status, debug registers


Push Buttons

The following table lists the push button functions and the corresponding board references in each FPGA board.

FunctionCyclone V GT Development Board ReferenceArria V GX Starter Board ReferenceStratix V GX Development Board ReferenceDescription
ResetS1S7S7Resets the demo design
Display configuration statusS3S5S5Displays the current Tx and Rx MSA values and link configuration in the Nios II terminal


LEDs

The following table lists the LEDs used in the design and the corresponding board references in each FPGA board.

FunctionCyclone V GT Development Board ReferenceArria V GX Starter Board ReferenceStratix V GX Development Board ReferenceDescription (when ON)
RX video lock statusD18D19D21Stable MSA values are received 15 times
RX lane count[4:0] status{D10,D11,D15,D16,D17}{D22,D23,D16,D17,D18}{D9,D10,D18,D19,D20}Current RX lane count: 5’b00001=1 lane, 5’b00010=2 lanes, 5’b00100=4 lanes
PLL lock statusD9D21D8Video clock, AUX clock, and transceiver reference clock have achieved lock
FPGA reset statusD8D20D7FPGA reset is asserted


Video and Image Processing

The Video and Image Processing block is part of the Qsys system in the design. It generates a test pattern and outputs processed video image to the DisplayPort IP core (Source). The following Video and Image Processing (VIP) suite IP cores are used:

  • Test Pattern Generator – Generates color bar pattern for background image
  • Clocked Video Output – Converts Avalon-ST Video protocol to DP Source video input format

The figure below shows the video IP connection in the Qsys system.

e/e3/Tx_only_vip.png ( Tx only vip.png - click here to view image )


TX Tranceivers

The transceiver is excluded from the DisplayPort IP core in Quartus 14.0. Separating the transceiver from the DisplayPort IP core enables flexibility for system design and allows the transceiver PHY to be shared with other display interface IP, if needed.

The Quartus IP Catalog provides a transceiver Native PHY library that includes the transceivers configured for DisplayPort application. DisplayPort transceiver Native PHYs in the IP Catalog are based on the maximum link rate and transceiver parallel bus width.

Maximum link rate:

  • HBR2 (5.4Gbps)
  • HBR (2.7Gbps)
  • RBR (1.62Gbps)

Transceiver parallel bus width:

  • Dual Symbol (20-bit wide)
  • Quad Symbol (40-bit wide)

In Quartus 14.0 and later releases, a single reference clock frequency is supported to generate all link rates. The reference clock frequency used in the DisplayPort transceiver Native PHY libraries is 135MHz.


Tranceiver Reconfiguration

TX transceivers are reconfigured when DP Source and Sink auto-negotiate the link configuration during link training:

  • TX link rate
  • TX output voltage swing (VOD) and Pre-emphasis level

The following is a list of RTL modules for transceiver reconfiguration. All RTL modules except for the transceiver reconfiguration controller IP are provided in clear-text.

  • <device>_xcvr_reconfig.v – Transceiver reconfiguration controller IP. <device>: sv for Stratix V, av for Arria V, cv for Cyclone V
  • reconfig_mgmt_hw_ctrl.v – Top level reconfiguration management FSM that handles reconfiguration request from the DisplayPort IP core
  • reconfig_mgmt_write.v – Generates Avalon-MM write cycles to the transceiver reconfiguration controller
  • dp_mif_mappings.v – Maps DP link rate to the transceiver PLL settings
  • dp_analog_mappings.v – Maps DP VOD and Pre-emphasis levels to the transmitter analog settings


4K Support

4K (3840x2160) resolution is supported with some minor changes to the system.

The VIP Suite components must be upgraded to TPG II and CVO II variants. These will replace the older IPs starting in 14.1. In mean-time, they are both available in the IP catalog.

When running a design at 3840x2160 @60Hz, the pixel clock is 533MHz / 4 = 133MHz for quad pixel mode

Here are the parameters that must be changed:


DisplayPort IP Core
  • Pixel Input Mode: Quad

Test Pattern Generator II (TPG II)
  • Maximum Frame Width: 3840
  • Maximum Frame Height: 2160
  • Pixels in Parallel: 4

Clocked Video Output II (CVO II)
  • Image Width/Active Pixels: 3840
  • Image Height/Active Pixes: 2160
  • Number of Pixels in Parallel: 4
  • Horizontal Sync: 88
  • Horizontal Front Porch: 176
  • Horizontal Back Porch: 296
  • Vertical Sync: 10
  • Vertical Front Porch: 8
  • Vertical Back Porch: 72
  • Pixel FIFO Size: 3840
  • FIFO level at which to start output: 3839


Demo Walk-through

References

Altera DisplayPort MegaCore Function User Guide

Altera Transceiver PHY IP Core User Guide

Altera Video and Image Processing Suite User Guide

Altera Nios II Software Developer's Handbook


Download Designs

DisplayPort TX-Only Design Example for Stratix V GX FPGA Development Kit

DisplayPort TX-Only Design Example for Arria V Starter Kit

DisplayPort TX-Only Design Example for Cyclone V GT FPGA Development Kit

4K Displayport TX-Only Design Example for Stratix V GX FPGA Development Kit

4K Displayport TX-Only Design Example for Arria V Starter Kit


History

DateChanges
Sept 25th, 2014Page Created
October 10th, 20144K design uploaded


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‎06-27-2019 10:27 PM
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