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DisplayPort MegaCore Debug Checklist

DisplayPort MegaCore Debug Checklist


Introduction

This document describes the hardware debug flow and provides a checklist when testing out the Altera DisplayPort MegaCore. These guidelines help you verify your design, identify the problems, and resolve them quickly.


The following diagram shows an overview of the hardware debug flow. 

1/18/Debug_flow.jpg ( Debug flow.jpg - click here to view image )


General Debug Checklist


1. Verify that the DP core clocks active and running at the correct frequency range as shown below.

PortDescriptionFrequency
clkAvalon-MM Controller InterfaceTypical range is 100~125 MHz when the clock source is shared with 'xcvr_mgmt_clk'
xcvr_mgmt_clkTransceiver management clock for reconfigurationSame as 'clk'
aux_clkAUX channel controller16 MHz
xcvr_ref_clk[0]Transceiver reference clock for 1.62 Gbps link rate162 MHz
xcvr_ref_clk[1]Transceiver reference clock for 2.7 and 5.4 Gbps link rate270 MHz
tx_vid_clkSource pixel clockSource pixel clock frequency depends on the video resolution and pixel mode
rx_vid_clkSink pixel clockSink pixel clock frequency depends on the video resolution and pixel mode



2. Verify the external clock inputs are active, clean, and mapped to the correct pins, IO_STANDARD, and use proper termination. 

3. Verify that the DP signals are mapped to the correct pins and IO_STANDARD. Make sure the Main Link and AUX channel signals use proper termination as per the specification. 

4. Verify the Main Link and AUX Channel differential signals are routed using the correct polarity at the board level connection. DisplayPort parameter editor allows user to invert the Main Link transceiver polarity. 

5. Verify that the design has met the timing constraints in all operating conditions. 

6. Check the power supply voltages are clean and at the correct levels.


Link-up Debug Checklist

  1. Unplug and re-plug the cable. This will cause the link to be re-trained. Make sure the cable is properly seated into the connector.
  2. Verify the HPD signal is properly asserted when the cable is plugged. Check if DP core tx_hpd / rx_hpd internal node in SignalTap is asserted. Monitor the HPD signal level on the scope and make sure it meets the HPD signal specifications in DP1.2a Ch. 3.3 Hot Plug/Unplug Detect Circuitry.
  3. Make sure the source AUX channel differential pair has the pullup/pulldown resistors to assist detection of DP source and powered DP source by the sink. For details about the pullup/pulldown resistors, refer to the description in the DP1.2a Ch. 3.4 AUX Channel.
  4. Verify the AUX channel signals meet the electrical specifications as per DP1.2a Ch. 3.4.2 AUX Channel Electrical Sub-block. Monitor the signals on the scope. Make sure the signals are properly terminated.
  5. Make sure the source IRQ to the embedded controller is enabled. Read DPTX_TX_CONTROL register and verify that HPD_IRQ_EN bit in the DPTX_TX_CONTROL register is set to 1.
  6. Verify the AUX transaction requests and replies are properly exchanged during link training. Monitor AUX traffic using a test equipment. Or connect an Avalon-ST FIFO to DP core AUX debug port and monitor the traffic in a nios2 terminal.
  7. Verify the transceiver TX/RX link rate and TX analog reconfiguration works properly in SignalTap. Make sure the reconfiguration control handshaking between DP core and reconfiguration controller occur as shown in the simulation example in the DP user guide. Note that if external redriver is used, TX analog reconfiguration needs to be disabled.
  8. Verify in SignalTap that the transmitter PLL lock signal, pll_locked, stays asserted. Make sure the source transceiver reference clock jitter is within the specification.
  9. Verify in SignalTap that the sink’s receiver CDR locks to incoming serial data. If locked, then the ‘rx_is_lockedtodata’ stays asserted.
  10. Make sure the source’s transmitter VOD and pre-emphasis settings are adequate. Make sure the Main Link TX EYE opening measured at the receiver is within the specifications. If not, adjust the VOD and/or pre-emphasis and verify that TX jitter is within the specifications.
  11. Make sure the sink’s receiver DC gain (XCVR_RX_DC_GAIN) and AC gain (XCVR_RX_LINEAR_EQUALIZER_CONTROL) settings are fine-tuned for optimal performance. Refer to the target device datasheet for AC gain curve graph.


Video Debug Checklist

If the video is not properly displayed, check the following.


Source

  1. Make sure the source reads EDID data properly via AUX channel. Verify the sink's EDID content includes the support for the source video resolution and timing.
  2. Read the source Main Stream Attribute (MSA) registers and verify the MSA values match the input video attributes. Verify the source tx video interface (tx_video_in) signal timing in SignalTap. For details about the source MSA registers and tx video interface signals, refer to the DP user guide.
  3. Make sure the link bandwidth is not oversubscribed by the TX video data. The link bandwidth determined by the source link policy maker should be greater than the video data bandwidth. The bandwidths are calculated as follows.
  • Effective link bandwidth (Gbps) = 0.8 * (enabled lanes * link rate)

- bandwidth prior to 8b/10b encoding

  • Video data bandwidth (Gbps) = (total horizontal pixels * total vertical lines * refresh rate * bits per pixel) / 1000

- total horizontal pixels: number of pixels including active video and blanking

- total vertical lines: number of lines including active video and blanking


4. Verify the pixel clock frequency, color depth setting, Hsync/Vsync timing parameters, and video resolution. 

5. Verify the link bit error rate is within the specifications.


Sink

  1. Verify the sink EDID memory content. Onchip EDID memory can be read by clicking ‘Tools -> In-System Memory Content Editor’ in Quartus software. Make sure the EDID content includes the support for the source video.
  2. Read the sink Main Stream Attribute (MSA) registers and verify the MSA values match the source video attributes. Monitor the sink rx video interface (rx_video_out) signal timing in SignalTap. For details about the sink MSA registers and rx video interface signals, refer to the DP user guide.
  3. Verify in SignalTap that ‘rx_vid_overflow’ is not asserted. The ‘rx_vid_overflow’ is asserted for at least one clock cycle when the sink internal video data FIFO runs into an overflow condition. This condition can occur when the sink video clock frequency is too low to transport the received video data successfully.
  4. Verify the pixel clock frequency, color depth setting, Hsync/Vsync timing parameters, and video resolution.
  5. Verify the link bit error rate is within the specifications.
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‎06-26-2019 05:08 AM
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