This document describes the hardware debug flow and provides a checklist when testing out the Altera DisplayPort MegaCore. These guidelines help you verify your design, identify the problems, and resolve them quickly.
The following diagram shows an overview of the hardware debug flow.
1. Verify that the DP core clocks active and running at the correct frequency range as shown below.
|clk||Avalon-MM Controller Interface||Typical range is 100~125 MHz when the clock source is shared with 'xcvr_mgmt_clk'|
|xcvr_mgmt_clk||Transceiver management clock for reconfiguration||Same as 'clk'|
|aux_clk||AUX channel controller||16 MHz|
|xcvr_ref_clk||Transceiver reference clock for 1.62 Gbps link rate||162 MHz|
|xcvr_ref_clk||Transceiver reference clock for 2.7 and 5.4 Gbps link rate||270 MHz|
|tx_vid_clk||Source pixel clock||Source pixel clock frequency depends on the video resolution and pixel mode|
|rx_vid_clk||Sink pixel clock||Sink pixel clock frequency depends on the video resolution and pixel mode|
2. Verify the external clock inputs are active, clean, and mapped to the correct pins, IO_STANDARD, and use proper termination.
3. Verify that the DP signals are mapped to the correct pins and IO_STANDARD. Make sure the Main Link and AUX channel signals use proper termination as per the specification.
4. Verify the Main Link and AUX Channel differential signals are routed using the correct polarity at the board level connection. DisplayPort parameter editor allows user to invert the Main Link transceiver polarity.
5. Verify that the design has met the timing constraints in all operating conditions.
6. Check the power supply voltages are clean and at the correct levels.
If the video is not properly displayed, check the following.
- bandwidth prior to 8b/10b encoding
- total horizontal pixels: number of pixels including active video and blanking
- total vertical lines: number of lines including active video and blanking
4. Verify the pixel clock frequency, color depth setting, Hsync/Vsync timing parameters, and video resolution.
5. Verify the link bit error rate is within the specifications.