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Dynamic I/O Delay Chain for Stratix V

Dynamic I/O Delay Chain for Stratix V



Dynamic I/O Delay Chain for Stratix V

StratixV I/O dynamic delay chain design example is the extension to the Stratix IV version. This design example aims to show how to configure for StratixV dynamic I/O delay chain which is different from StratixIV like the configuration cycles, position of LSB and MSB bits, position for output/input/reserved bits. Attached is the QuartusII design and user manual.

File:Dynamic IO Delay Chain (StratixV).zip

a/a5/StratixIV_dynamic_delay_chain_config_bits.PNG ( StratixIV dynamic delay chain config bits.PNG - click here to view image )

5/54/StratixV_dynamic_delay_chain_config_bits.PNG ( StratixV dynamic delay chain config bits.PNG - click here to view image )

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Last update:
‎06-26-2019 05:10 AM
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