cancel
Showing results for 
Search instead for 
Did you mean: 
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Dynamic I/O Delay Chain for Stratix V

Dynamic I/O Delay Chain for Stratix V



Dynamic I/O Delay Chain for Stratix V

StratixV I/O dynamic delay chain design example is the extension to the Stratix IV version. This design example aims to show how to configure for StratixV dynamic I/O delay chain which is different from StratixIV like the configuration cycles, position of LSB and MSB bits, position for output/input/reserved bits. Attached is the QuartusII design and user manual.

File:Dynamic IO Delay Chain (StratixV).zip

a/a5/StratixIV_dynamic_delay_chain_config_bits.PNG ( StratixIV dynamic delay chain config bits.PNG - click here to view image )

5/54/StratixV_dynamic_delay_chain_config_bits.PNG ( StratixV dynamic delay chain config bits.PNG - click here to view image )

Attachments
Version history
Last update:
‎06-26-2019 05:10 AM
Updated by:
Contributors