EMIF Implementation differences between Intel Agilex® FPGA and previous FPGA families
For users who may be familiar with Intel® Arria® 10 FPGA or Intel® Stratix® 10 FPGA External Memory Interface (EMIF) IP and might expect similar features and implementation flows for Intel Agilex® FPGA EMIF IP, this article informs users of the important differences they need to be aware of when starting a new Intel Agilex® FPGA EMIF design. For further information on these points, refer to the External Memory Interfaces Intel Agilex® FPGA IP User Guide.
(1) Intel Agilex FPGA EMIF IP does not support PHY only, and ping-pong PHY configurations
(2) Intel Agilex FPGA uses IO-96 I/O banks which are comprised of two I/O 48 sub-banks named top and bottom
(3) Intel Agilex FPGA requires a single calibration IP component to be instantiated for interfaces on each device edge
- Select the number of interfaces to be supported
- Connect the calibration bus and clock to each DDR4 IP
(4) Intel Agilex FPGA DM/DBI pin is in a fixed location in an x8 DQS group
(5) Intel Agilex FPGA EMIF PLL reference clock differential I/O standard is “True Differential signaling”
- It may require external components for DC bias and AC coupling
(6) Intel Agilex FPGA EMIF I/O timing flow is new
- No EMIF IP Board tab parameters of signal group skews are required
- Intel provides collateral on the DDR4 interface recommendations for PCB layout
- The customer runs Board simulations (SPICE), and the waveform eye diagram is compared to a mask for verification of the Intel Agilex FPGA I/O timing and PCB layout
(7) Intel® Quartus® Prime Software Timing Analyzer still has “Report DDR,” but this only covers internal EMIF IP timing :
- Reset/Recovery
- Core to core, core to periphery, periphery to core.
(8) Intel Agilex FPGA EMIF Debug toolkit is in the Intel® Quartus® Prime Edition Software Unified Toolkit (UTK)
- Similar features to the Intel Arria 10 FPGA/Intel Stratix 10 FPGA legacy EMIF Toolkits
- Configurable Traffic generator 2.0 has more flexible functionality for debugging, which can be modified without having to recompile the project
- Preset traffic patterns
- User-defined traffic patterns
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2021-06-27
David Elmer
