Become a system architect by creating an entire Nios II based processor system in 3 hours or less.
This lab is a great tool if you are new to developing embedded systems on FPGAs and explains not only the "how" but also the "why". The lab targets DE1 hardware but you dont need the hardware to build the lab, only to test it.
1. Lab Design Files (free download)
a. Lab Instruction Workbook v9.1 PDF Doc (4MB)
Note: The Filtering section of the Clock in the document does not refer to adding of a CLOCK which is mentioned in the 9.0 Workbook. Refering the section 4.4 in 9.0 would be apt to avoid confusion.
1. Lab manual and design files (free download)
a. Lab Instruction Workbook v9.0
b. Instructions on how to 'unlock' cool beta features in SOPC Builder v9.0 click here
c. Instructions on how to 'unlock' cool beta features in SOPC Builder v9.0sp1 and beyond click here
2. Quartus II and Nios II EDS v8.1 or above (Download free Web Edition)
3. Cyclone II Starter Kit (optional if you would like to see the system actually run on hardware)
For questions and feedback contact embedded_lab@altera.com.
1. Lab manual and design files (free download)
2. If you would like to download just the manual custom paper then click here
2/2a/DesignFlow.jpg ( DesignFlow.jpg - click here to view image ) Design flow diagram
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