Embedded Systems Lab

[#1]

Embedded Systems Lab

Become a system architect by creating an entire Nios II based processor system in 3 hours or less.

This lab is a great tool if you are new to developing embedded systems on FPGAs and explains not only the "how" but also the "why". The lab targets DE1 hardware but you dont need the hardware to build the lab, only to test it.

Topics covered

• Designing the system with an explanation of design flow, requirements, and strategy
• Setting up a Quartus II project
• Building the SOPC System with SOPC Builder
• Building the software application with the Nios II Embedded Design Suite
• Lab validation to provide feedback on the usefulness of this lab

New Lab requirements v9.1

1.     Lab Design Files (free download)

a.     Lab Instruction Workbook v9.1 PDF Doc (4MB)

Note: The Filtering section of the Clock in the document does not refer to adding of a CLOCK which is mentioned in the 9.0 Workbook. Refering the section 4.4 in 9.0 would be apt to avoid confusion.

1. Quartus II and Nios II EDS v9.1 or above (Download free Web Edition)
2. Cyclone II Starter Kit (optional if you would like to see the system actually run on hardware)

Lab requirements v9.0

1.     Lab manual and design files (free download)

a.     Lab Instruction Workbook v9.0

b.     Instructions on how to 'unlock' cool beta features in SOPC Builder v9.0 click here

c.     Instructions on how to 'unlock' cool beta features in SOPC Builder v9.0sp1 and beyond click here

2.     Quartus II and Nios II EDS v8.1 or above (Download free Web Edition)

3.     Cyclone II Starter Kit (optional if you would like to see the system actually run on hardware)

For questions and feedback contact embedded_lab@altera.com.

Using Quartus II/Nios II EDS v8.1? No problem, get the v8.1 of the Lab

1.     Lab manual and design files (free download)

2.     If you would like to download just the manual custom paper then click here

f/fa/SystemSketch.jpg ( SystemSketch.jpg - click here to view image ) Sketch of the system you build in the lab

 2/2a/DesignFlow.jpg ( DesignFlow.jpg - click here to view image ) Design flow diagram

 5/50/Fig1-cyclone2-staterkit.jpg ( Fig1-cyclone2-staterkit.jpg - click here to view image ) Target hardware