Please refer to the <ProjectRoot>/altera_ink_esc/GettingStartedEtherCATAcessIP.pdf document in the delivered IP. It provides a complete description of the reference design, compiling and debugging the firmware, programming the EtherCAT EEPROM, installing the TwinCAT PLC software and running the PLC program.
The EtherCAT reference design was developed and tested with Quartus II software version 13.0. Any other version of Quartus may or may not work as expected, and no support is available for any other version of Quartus for this development kit.
You can use The TwinCAT 3 PLC software available from Beckhoff. Download from TwinCAT 3 Download or any EtherCAT PLC.
Ensure that your Quartus license path (Tools -> License Setup) includes both Softing's and Beckhoff's license files. The required license files are provided in the delivered IP.
Softing's license file is in:
Beckhoff's is in:
In addition, you will need a NIOS II license to build the out-of-box design, which can be acquired from Altera. The NIOS II IP core can be used in a limited, unlicensed mode using Altera's Open Core Plus (OCP), which allows for unlimited usage as long as the device is connected to a licensed Quartus tool (i.e. tethered to a computer) or in a time-limited capability if untethered.
Go to the Design for Multiple Industrial Ethernet Protocols web page for instructions on how to obtain a permanent license.
If the design is working properly without a PLC, the LEDs on the INK board will flash immediately after rebooting the INK, and LCD screen wil display
Follow the instructions in the <ProjectRoot>/altera_ink_esc/GettingStartedEtherCATAcessIP.pdf document, to determine if the design is working as expected with a PLC.
Note that the delivered IP core is set up with a 15 minute time-bomb license. You can run the demo application for 15 minutes without any license or authentication CPLD attached.
This following section describes IP authentication for short-term development and how to authenticate the IP beyond the 15 minute maximum operational time.
The Softing EtherCAT IP uses an Altera MAX II CPLD as a security chip to ensure that only authorized instantiations of the IP are allowed. However, to facilitate evaluation and development of the IP, a 15 minute evaluation period is integrated into the design, allowing the system to run without the security chip until the 15 minute window expires. Once this window expires, a power cycle of the INK will trigger a new 15 minute evaluation period. Once the 15 minute window expires and no CPLD is attached to the IP, the IP no longer communicates with the PLC or passes traffic through the Ethernet ports.
The delivered IP contains a temporary EtherCAT Vendor ID package for testing purposes. The value of this Vendor ID is 0xEEEEEEEE. You need to replace this temporary Vendor ID with your own to allow the Softing EtherCAT IP to run longer than the 15 minute window.
Here are the step you need to take:
With the daughter card attached to the INK board and the re-compiled IP with your Vendor ID, the system will run beyond the 15 minute window.
Details of this daughter board and its debug features can be found in the "CPLD Daughter Card" section that follows.
The Softing EtherCAT IP has a built-in time limit that will allow it to run for a 15 minute evaluation period, but to run longer, a preprogrammed Altera CPLD must be connected to the Softing IP and the IP must be recompiled with your own Vendor ID. An Altera MAX II development kit containing a programmed CPLD is available from your Altera representatives.
This kit has the Softing security chip, but also some additional debug features to help you to confirm the authentication challenges and responses are correct. The next section describes those features.
The Altera MAX II development kit comes with pushbuttons and LEDs. These are listed in the following table with the corresponding features for the CPLD Security design.
|Board Label||Brief Name||Color||Details|
|led1||Out of Reset||Red||Indicates the daughter card is out of reset. The system will come out of reset on its own, but it can be placed back into reset using a push button.|
|led2||Clock Toggling||Red||This led will pulse approximately twice a second and is an indicator the clock on the board is working.|
|led3||Challenge Valid||Red||Indicates the Softing IP is sending a challenge request to the CPLD.|
|led4||Response Valid||Red||Indicates the CPLD is sending a response to the Softing IP.|
|button1||rst_system_n||--||If needed, the CPLD can be held in reset if this button is pressed. Generally, the system should not require a reset.|
|button2||Insert Error||--||When this button is pressed and then released, internal logic then waits until the next authentication challenge is sent. When this occurs, the response is purposely corrupted forcing the Softing IP to attempt a challenge retry. This can be observed as second set of pulsing LED3 and LED4.|
After the 15 minute window has expired, the IP issues a new challenge to the CPLD approximately once a minute.
The normal challenge and response will cause LED3 to pulse briefly followed by LED4 pulsing briefly. LED3 indicates the Softing IP is issuing a challenge request and the LED4 indicates the CPLD is issuing a response. Each pulse lasts less than half a second. If the Softing IP detects a bad response, it will immediately issue another challenge request. If it continues getting bad responses it will repeat this sequence until the retry timeout occurs (four pulses) and then abort trying to authenticate.
So, by observing the number of LED pulses, you can determine if the challenge and response was correct (one pulse of each LED), or if the challenge response was bad (several pulses of the LEDs). To demonstrate this in steps:
|LED4 Pulses Counted||State||Details|
|0||Unknown||This could indicate the daughter card is not connected correctly or some kind of connection issue.|
|1||Authorized||This is the common, correct authorized state.|
|2||Authorized with one error||This indicates that one challenge was sent and the response was incorrect but a second challenge yielded a good response. This can happen as part of the Insert Error functionality (button2, above) or due to random noise on the connectors. The system is in an authorized state.|
|3 or greater||Unauthorized||This indicates the CPLD is not programmed with the Softing security key. Contact your Altera representative to get the correct board. The system will continue to run for the 15 minute window.|
Since the first challenge occurs very quickly after the INK powers up and the FPGA configures, it may be possible that noise on the FPGA I/O during this time may make counting either of the LED3 or LED4 pulses difficult. If this is the case, the best solution is to use the Insert Error feature by pressing button2 in between steps 2 and 3 above. When the INK is powered up, the first challenge will be given a bad response which will cause a second challenge to be issued. This makes it easier to differentiate a set of LED3/4 pulses due to challenge/response verses noise causing random looking pulses.
The challenge/response sequence (LED3/4) can be also observed after the 15 window. The exchange should happen periodically, approximately once every minute.
The EtherCAT reference design from Softing has a time limitation that allows the design to run for 15 minutes, then it stops functioning as expected. Please contact Softing for licensing information.