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Extending Avalon-MM via LVDS

Extending Avalon-MM via LVDS

The Avalon Memory-Mapped (Avalon-MM) interface is a control-plane interface that can easily be mapped to most peripherals. It can range from an extremely simple localbus interface, to a complex pipelined interface, capable of handling variable latency burst transactions. This reference design of parameterizable IP blocks allows the Avalon-MM interface to be extended across a high-speed LVDS interface between a set of devices. This might be done for various reasons, such as to simply extend the control plane, or to expand the I/O interface of a device for lower-speed signals.

5/5b/AVMM2LVDS.png ( AVMM2LVDS.png - click here to view image )

Avalon-MM via LVDS Block Diagram

This archive contains the parameterizable Qsys IP blocks, as well as an example reference design that interfaces the Cyclone V SoC and Max 10 FPGA Development Kits.

File:AVMM via

File:AVMM via LVDS.pdf

Keywords: IO expansion, I/O expansion, Avalon-MM, AVMM, LVDS

Version history
Last update:
‎06-26-2019 11:44 PM
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