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This design is based on design example provided in https://www.altera.com/support/support-resources/design-examples/design-software/opencl/fft-1d.html
The design has been modified from 8-Parallel FFT to 4-Parallel FFT in order for it to be able to fit into Cyclone V SOC device. This design is verified in both simulation and hardware which it can performed around 9Gflops.
For more complete information about compiler optimizations, see our Optimization Notice.