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FIFOed Avalon Uart

FIFOed Avalon Uart

Last Updated

Aug 19, 2014


This component is an upgraded version of the Altera Avalon UART. Its most important feature is the ability to include FIFOs for the rx and tx paths. These FIFOs are configurable in size. Also included in this version is the ability to set the irq threshold for both the rx and tx paths, as well as a timeout feature to keep characters from getting orphaned in the rx FIFO. New in 9.3 is a timestamp feature and gap detection, along with the ability to include error and status info in the rx_fifo. Version 9.3 is compatible with the new IRQ/ISR calls in the 9.1 tool. Version 13.1 is compatable with quartus 13.1 and higher.


To be filled in...


The document describes more details of the FIFOed Avalon UART. The zip file includes Tcl scripts and perl scripts for the creation of the component. There are three subdirectories:

  • Getopt – needed for generation,
  • HAL – all the source and include files for operation, and
  • inc – the standard definitions of the registers.


The FIFOed UART can be placed in one of several places. When you unzip make sure you don’t have nested folders named Fifoed_avalon_uart9.x inside one another.

1- Place the folder FIFOed_avalon_uart in to the standard components directory


SOPC Builder will automatically search for components in any subdirectory under the IP directory. Do not place the files in the Altera subdirectory this has a fixed mapping.

2- Or you can place it in the ip subdirectory under your current project.

3- You can also place it anywhere else you want but you will need to tell SOPC Builder the path (in Tools/options). The BSP Editor will need to have the path as well

Then next time you launch SOPC Builder you will have a new component in Interface Protocols/Serial called Fifoed Uart(RS-232 serial port)13.1

NOTE: I have seen cases where the 9.3 version will not build. This has mainly been due to the fact the the file fifoed_uart_log.bat file was not present. This could be due to the fact that the component was emailed and the emailer stripped out the .bat file. In any case the .bat file is only needed for simulation but will cause a build error if not present. Here is the content of the file

@ start "jtag_uart_output_stream.dat" cmd /t:06 /c %1%/perl -- jtag_uart_output_stream.dat


  • There are Altera HAL drivers included in the package.


This version of the component will only work with Quartus 9.0 and later.

See Also

Altera Avalon Uart documenation

New Features in version 9.3

  1. Included break, pe,fe, and oe in the fifo data so knwoledge can be preserved about when theses errors occur.
  2. Included timestamps for incoming data as well as timout irq so you can detect gaps between transmissions.

New Features in version 13.1

  1. Updated the perl code to more closely match the Altera_Avalon_Uart.
  2. Updated to support the 13.1 hw.tcl format
  3. primarily a compatability release

Future Release

  1. What would you like to see in future release?

When using the FIFOed UART (RS-232 serial port)13.1 in Qsys, when I check the "Export FIFO used signals" box in the MISC tab, I get an error saying "add_interface_port: No interface g1 while executing "add_interface_port g1 rxused..." Please help.

  1. I have thought about adding an additional 2 registers that can be read to determing the rx/tx fifo size

Update History

20130317- Unofficial patch: I fixed a bug in fifoed_avalon_uart_read() that was preventing O_NONBLOCK mode from working properly. I also modified fifoed_avalon_uart_hw.tcl to pass the input frequency (needed for baud rate calculations) and parity (for info only) through to system.h. 20100611- Fixed bugs added timestamp, Gap, and fifo status bits. 13.2 - fixed the gap timer export


Version history
Last update:
‎06-26-2019 11:47 PM
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