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FTA Board Update Portal based on Nios II Processor with EPCQ

FTA Board Update Portal based on Nios II Processor with EPCQ


Last Major Update 

October 10, 2016

 

Introduction

Fault Tree Analysis (FTA) uses tree structures to decompose system level failures into combinations of lower-level events, and Boolean gates to model their interactions. The objective of this debug FTA example is to help troubleshoot and identify issue related to Board Update Portal based on Nios II Processor with EPCQ design example and resolve it effectively. 


Fault Tree Analysis Diagram & Table

The FTA example : FTA_board_update_portal_niosii_epcq consists of a FTA diagram and table used to debug and root cause the Board Update Portal design example failed to run issue. In the FTA diagram, multiple hypothesis are made based on the failure symptom as described. For each of the hypothesis, it can have second level or up to third level suspects. The FTA diagram will then be converted into a table format to proper keep track of the debug progress. In the FTA table, for every suspect listed, it needs to have some action items to be performed to verify it together with some additional category information to be filled in such as Owner, Target Completion Date, Status/Results, Possible Next Step and Priority level.

Disclaimer

© [2016] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 11:54 PM
Updated by:
 
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