FTA PCI express
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FTA PCI express
Last Major Update
November 7, 2017
Introduction
Fault Tree Analysis (FTA) uses tree structures to decompose system level failures into combinations of lower-level events, and Boolean gates to model their interactions. The objective of the PCIe link training FTA is to provide the techniques required to troubleshoot the PCIe link training issue with Arria 10 device and resolve it effectively.
Fault Tree Analysis (FTA) for Arria 10 PCIe Link Up Issue
Some of the common PCIe link training issues are:
i) LTSSM failed to reach/stay stably at L0.
ii) Link failed to negotiate to expected speed.
iii) Link failed to negotiate to the expected width.
FTA File Download
FTA File Tour
This FTA consists of five different tabs:
Tab 1 - First level debug:
First level debug steps which lead you to the correct hypothesis/debug steps in FTA_Table_View tab or FTA_Diagram_View tab.
3/3f/Tab1.png ( Tab1.png - click here to view image )
First level debug
Tab 2 - FTA_Table_View:
The comprehensive debug steps in table form to debug the Arria 10 PCIe link up issue.
9/94/Tab2.png ( Tab2.png - click here to view image )
FTA_Table_View
Tab 3 - FTA_Diagram_View:
The comprehensive debug steps in Diagram form to debug the Arria 10 PCIe link up issue.
0/08/Tab3.png ( Tab3.png - click here to view image )
FTA_Diagram_View
Tab 4 - HIP_PIPE_Interface_Signals:
Procedure to monitor PCIe PIPE interface signals in HIP
6/62/Tab4.png ( Tab4.png - click here to view image )
HIP_PIPE_Interface_Signals
Tab 5 - Diagram:
Examples/diagram of the debug steps stated in FTA_Table_View
2/27/Tab5.png ( Tab5.png - click here to view image
Diagram
Disclaimer
© [2013] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.
