Variable Precision DSP in Altera's 28nm FPGA is well suited for floating point implementation. This Matrix Inversion design example validates Altera's floating point capability by showing both performance and efficiency. It uses Stratix IV and Arria II GX FPGAs to build largest matrix inversion possible, scale down, and then show tool's capability.
Cholesky decomposition, with forward and back substitution
Stratix IV FPGA (vector size = 60)
Arria II GX FPGA (vector size = 30)
This table shows the performance of the Cholesky decomposition design example.
Download design example file and request documentation.