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Floating-point Matrix Inversion Example

Floating-point Matrix Inversion Example


Overview

Variable Precision DSP in Altera's 28nm FPGA is well suited for floating point implementation. This Matrix Inversion design example validates Altera's floating point capability by showing both performance and efficiency. It uses Stratix IV and Arria II GX FPGAs to build largest matrix inversion possible, scale down, and then show tool's capability.

  • Cholesky decomposition, with forward and back substitution
  • Stratix IV FPGA (vector size = 60)
  • Arria II GX FPGA (vector size = 30)


This table shows the performance of the Cholesky decomposition design example.



Download

Download design example file and request documentation.

Design File

Documentation

Cholesky decomposition design example (v11.0)

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Cholesky decomposition design example (v11.1)

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  • Send request to floatingpoint@altera.com. Please include your target end-application and office location in your request.

Contact

Please contact floatingpoint@altera.com for latest reference design with performance improvement. 

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Revision #:
1 of 1
Last update:
‎06-27-2019 12:29 AM
Updated by:
 
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