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High-Speed Transceiver Demo Designs - Stratix 10 GX Series

High Speed Transceiver Demo Designs - Stratix 10 GX Series

Index

Stratix 10 LVDS Test Designs

1. LVDS PHY

 

Stratix 10 GX

1. Script with useful procedures for use in system console for Stratix 10 GX (L/H-Tile Production)

2. Library of C-functions for transceivers/plls using AVMM Interface for Stratix 10 GX (L/H-Tile Production)

3. Ultralite I

4. 100GbE Demo Designs

5. Transceiver Toolkit Designs and Soft PRBS Test Designs (inc. dynamic reconfiguration)

6. Ultralite II

7. Double Rate Transfer

8. KR-FEC

9. Superlite II

10. Superlite II Synchronous

11. Ultralite II Asynchronous

 

 

Stratix 10 LVDS Test Designs

1. LVDS PHY

  • NEW (26/03/2020) Fully parameterizable Stratix 10 LVDS Phy Module to transport a wide databus across multiple LVDS Lanes with DPA (inc. 4 channel Loopback Demo design for the S10GX SI board)

 

 

Stratix 10 GX

1. Script with useful procedures for use in system console for Stratix 10 GX (L/H-Tile Production)

 

2. Library of C-functions for transceivers/plls using AVMM Interface for Stratix 10 GX (L/H-Tile Production)

  • This library contains functions for :
    • Eye measurement (2D+1D) and Eye plot (2D+1D) (ODI_functions.c)
    • Configuring PMA settings and readout of all PMA settings (PMA_functions.c)
    • Calibrating the transceiver and PLLs (calibration_functions.c)
    • Configuring the Native Phy including reconfiguring Native PHY and PLL's (nphy_functions.c)
    • (note : these functions are used in the 64 Channel design available for download in section 2.5)

 

 

 

3. Ultralite I

  • (22/01/2018) Stratix 10 GX SI Board (H-Tile ES1): Ultralite I V2 demo design with auto-training and deskew using 8 lanes at 10 Gbps (8b10b) routed to the 2 QSFP+ modules (116 ns tx-rx latency) incl. TTK functionality and EyeQ +( NEW ALA Data Viewer for state-of-the-art Eye analysis)

 

  • (22/01/2018) Stratix 10 GX SI Board (H-Tile ES1): Ultralite I V2 demo design with auto-training using 8 times 1 lane at 10 Gbps (8b10b) routed to the 2 QSFP+ modules (112 ns tx-rx latency) incl. TTK functionality and EyeQ +( NEW ALA Data Viewer for state-of-the-art Eye analysis)

 

  • (23/01/2018) Stratix 10 GX PCIe Development Kit (H-Tile ES1): Ultralite I V2 demo design with auto-training using 4 times 1 lane at 10 Gbps (8b10b) routed to the QSFP+ modules (112 ns tx-rx latency) incl. TTK functionality and EyeQ +( NEW ALA Data Viewer for state-of-the-art Eye analysis)

 

4. 100GbE Demo Designs

  • (06/06/2019) Stratix 10 GX SI Board (H-Tile Production): Dual 100GbE Design with RSFEC and KR (AN/LT) example with NPDME + Nios + ( ALA Data Viewer for state-of-the-art Eye analysis ) allows testing of 2 100GbE Design example instances connected using up to 5 meter of DAC cable

 

  • (14/05/2019) Stratix 10 GX SI Board (H-Tile Production): Dual 100GbE Design with RSFEC example with ADME + Nios + ( ALA Data Viewer for state-of-the-art Eye analysis ) allows testing of 2 100GbE Design example instances connected using up to 5 meter of DAC cable

 

  • (29/03/2018) Stratix 10 GX SI Board (H-Tile ES1): Dual 100GbE Design with RSFEC example with ADME + Nios + ( ALA Data Viewer for state-of-the-art Eye analysis ) allows testing of 2 100GbE Design example instances connected using up to 5 meter of DAC cable

 

  • (16/01/2018) Stratix 10 GX SI Board (H-Tile ES1): Dual 100GbE Design example with ADME + Nios + ( ALA Data Viewer for state-of-the-art Eye analysis ) allows testing of 2 100GbE Design example instances connected using up to 5 meter of DAC cable

 

5. Transceiver Toolkit Designs and Soft PRBS Test designs (inc. Dynamic Reconfiguration)

  • NEW (05/06/2020) Stratix 10 GX SI Board (H-Tile Production  4x 24 Channel Soft PRBS Test design with all 96 channels running at 12.5 Gbps using 4 Native PHY's (with Nios system + EyeQ + temperature measurement + I2C + internal noise logic + PMA sweep + ( ALA Data Viewer for state-of-the-art Eye analysis)

 

  • NEW (07/05/2020) Stratix 10 GX SI Board (H-Tile Production  4x 16 Channel Soft PRBS Test design that allows to reconfigure channels from GXT rate at 25 Gbps to GX rate at 10 Gbps dynamically on all channels (and vice versa) (with Nios system + EyeQ + temperature measurement + I2C + internal noise logic + PMA sweep + ( ALA Data Viewer for state-of-the-art Eye analysis)

 

  • NEW (24/04/2020) Stratix 10 GX SI Board (H-Tile Production  4x 16 Channel Soft PRBS Test design with all channels at 25 Gbps using 4 PHY's with Nios system + EyeQ + temperature measurement + I2C + internal noise logic + PMA sweep + ( ALA Data Viewer for state-of-the-art Eye analysis)

 

  • Updated (01/04/2020) Stratix 10 GX SI Board (H-Tile Production  64 Channel TTK design with all channels at 25 Gbps using 4 PHY's with Nios system + EyeQ + temperature measurement + I2C + internal noise logic + PMA sweep + ( ALA Data Viewer for state-of-the-art Eye analysis)

 

  • NEW (01/04/2020) Stratix 10 GX SI Board (H-Tile Production): 96 Channel TTK design with all channels at 12.5 Gbps using 4 PHY's with Nios system + EyeQ + temperature measurement + I2C + internal noise logic + PMA sweep + ( ALA Data Viewer for state-of-the-art Eye analysis)

 

 

  • (29/11/2017) Stratix 10 GX SI Board (H-Tile ES1): 96 Channel TTK design with all channels at 12.5 Gbps using 4 PHY's with Nios system + EyeQ + temperature measurement + internal noise logic + PMA sweep

 

  • (29/05/2017) Stratix 10 GX SI Board (L-Tile ES1): 96 Channel TTK design using 4 PHY's with Nios system + EyeQ + temperature and voltage measurement + ODI Acceleration enabled

 

  • (05/04/2017) Stratix 10 GX PCIe Development kit(L-Tile ES1): 72 Channel TTK design with Nios system + EyeQ + temperature and voltage measurement.

 

6. Ultralite II

  • (29/05/2018) Stratix 10 GX SI Board (H-Tile ES1): Ultralite II V2 FEC demo design with auto-training using 8 lanes at 25.78125 Gbps routed to the 2 QSFP28 modules using hardened KR-FEC incl. TTK functionality and EyeQ +( NEW ALA Data Viewer for state-of-the-art Eye analysis)

 

  • (12/07/2018) Stratix 10 GX SI Board (H-Tile ES1): Ultralite II V2 demo design with auto-training using 8 lanes at 25.78125 Gbps routed to the 2 QSFP28 modules (107 ns tx-rx latency) incl. TTK functionality and EyeQ +( NEW ALA Data Viewer for state-of-the-art Eye analysis)

 

7. Double Rate Transfer

  • (28/11/2017) Stratix 10 GX SI Board (H-Tile ES1): 8 Channel Multi PRBS Test design at 12.5 Gbps using Double Rate Transfer Mode running core logic at 625 Mhz (Tested up to 15 Gbps with 5 meter DAC Cable running core logic at 750 Mhz) (incl. TTK functionality and EyeQ)

 

8. KR-FEC

 

9. Superlite II

 

  • NEW (07/04/2020) Stratix 10 GX SI Board (H-Tile Production): Superlite II V4 demo design using 8 lanes at 25.78125 Gbps routed to the 2 QSFP28 modules (incl. TTK functionality and EyeQ). V4 adds automatic lane re-ordering.

 

  • UPDATED (03/04/2020) Stratix 10 GX SI Board (H-Tile Production): Superlite II V3 demo design using 8 lanes at 25.78125 Gbps routed to the 2 QSFP28 modules (incl. TTK functionality and EyeQ)

 

  • UPDATED (14/11/2018) Stratix 10 GX SI Board (H-Tile ES1): Superlite II V3 demo design using 8 lanes at 25.78125 Gbps routed to the 2 QSFP28 modules (incl. TTK functionality and EyeQ)

 

 

10. Superlite II Synchronous

  • (13/04/2017) Stratix 10 GX SI Board (L-Tile ES1): Superlite II Synchronous demo design to transport fully transparently a 25.6 Gbps datastream using 4 lanes at 8 Gbps routed to FMC connector A (incl. TTK functionality and EyeQ)

 

11. Ultralite II Asynchronous

  • (11/10/2017) Stratix 10 GX SI Board (H-Tile ES1): Ultralite II Asynchronous demo design to transport 50 Gbps data using 4 lanes at 12.5 Gbps routed to FMC connector A (incl. TTK functionality and EyeQ)

 

 

 

Version history
Revision #:
2 of 2
Last update:
‎06-29-2020 03:09 AM
Updated by: