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How to debug HPS SPI using SignalTapII

How to debug HPS SPI using SignalTapII


Overview

This page introduces how to debug HPS SPI using SignalTap II. HPS Peripheral signals can route to FPGA Fabric. 

So, using the feature, you can observe the signal on SignalTap II without any measurement instrument such as Logic Analyzer and Digital Oscilloscope as below.

e/ec/HPS_SignalTap2_SPI_SignalTapII_Cap.png ( HPS SignalTap2 SPI SignalTapII Cap.png - click here to view image )

As shown in Figure 1, the bock diagram is for the sample design.

6/60/HPS_SignalTap2_SPI_block_digram.png ( HPS SignalTap2 SPI block digram.png - click here to view image )

Figure 1 – The block diagram


Requirements

  • Cyclone V SoC Development Kit Rev D
  • Windows/Linux
  • QuartusII v15.0
  • SoC EDS v15.0


Procedure to update Qsys

  • Copy /15.0/embedded/examples/hardwarecv_soc_devkit_ghrd folder to your workspace
  • Click Open project and select ‘soc_system.qpf’
  • Launch Qsys and open ‘soc_system.qsys’
  • Click hps_0 and open parameter
  • Click ‘Peripheral Pins’ Tab
  • Select FPGA for HPS SPIM1 and SPIS1
  • Click export columns and input signal name, and Click ‘Generate HDL’ button and close Qsys


Procedure to update top design and STP file

  • Modify ‘ghrd_top.v’ for loopback between SPIM1 and SPIS1


...................................


wire hps_cold_reset;

wire hps_warm_reset;

wire hps_debug_reset;

wire [27:0] stm_hw_events;


//***** Begin of adding the code *****


wire hps_spim1_rxd ;

wire hps_spim1_txd ;

wire hps_spim1_ss_n ;

wire hps_spim1_clk ;


//***** End of adding the code ******


// connection of internal logics

assign fpga_led_pio = fpga_led_internal;

assign stm_hw_events = {{18{1'b0}}, fpga_dipsw_pio, fpga_led_internal, fpga_debounced_buttons};


// SoC sub-system module

soc_system soc_inst (

.memory_mem_a (hps_memory_mem_a),

.memory_mem_ba (hps_memory_mem_ba),

.memory_mem_ck (hps_memory_mem_ck),

.memory_mem_ck_n (hps_memory_mem_ck_n),

.memory_mem_cke (hps_memory_mem_cke),


...................................


.hps_0_hps_io_hps_io_gpio_inst_GPIO43 (hps_gpio_GPIO43),

.hps_0_hps_io_hps_io_gpio_inst_GPIO44 (hps_gpio_GPIO44),


//****** Begin of adding the code *****


.hps_0_spim1_txd (hps_spim1_txd),

.hps_0_spim1_rxd (hps_spim1_rxd),

.hps_0_spim1_ss_in_n (1),

.hps_0_spim1_ssi_oe_n (),

.hps_0_spim1_ss_0_n (hps_spim1_ss_n),

.hps_0_spim1_ss_1_n (),

.hps_0_spim1_ss_2_n (),

.hps_0_spim1_ss_3_n (),

.hps_0_spim1_sclk_out_clk (hps_spim1_clk),

.hps_0_spis1_txd (hps_spim1_rxd),

.hps_0_spis1_rxd (hps_spim1_txd),

.hps_0_spis1_ss_in_n (hps_spim1_ss_n),

.hps_0_spis1_ssi_oe_n (),

.hps_0_spis1_sclk_in_clk (hps_spim1_clk),


//****** End of adding the code ********


.hps_0_f2h_stm_hw_events_stm_hwevents (stm_hw_events),

.clk_clk (fpga_clk_50),

  • Click ‘Analysis & Synthesis’
  • Click Tools -> ‘SignalTap II Logic Analyzer’ menu
  • Click anywhere on Setup Tab
  • Find SPI signals using ‘Node Finder’
  • Insert selected signals to Signal Tap II and close this dialog
  • Click ‘Compile Design’ for full compiling


Setup Preloader

  • Launch embedded_command_shell.bat in /15.0/embedded folder
  • Move to workspace/software
  • Type ‘bsp-editor&’
  • Click File -> ‘New HPS BSP..’ Menu and open New BSP Dialog
  • Click Browse button, select your handoff file(/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0) and click ‘ok’ button
  • Click ‘Advanced’, check ‘SDRAM_SCRUBBING’ option and click ‘Generate’ button


Build preloader & import test software

  • Type ‘cd spl_bsp’ and ‘make’
  • Type ‘eclipse&’ for launching DS-5
  • Select your workspace ./software folder
  • Select File -> Import… menu
  • Select “Existing Projects into Workspace”, and click “Next” button.
  • Click “Browse..” button, select “How_To_Debug_SPI_With_SignalTapII.tar.gz”, and click “Finish” button
  • Right click on Project and select “Build Project” menu


Debug Configuration & Execution

  • Right Click , Select “Debug As” -> “Debug Configuration” menu.
  • Confirm Debug Settings and Click “Browse..” Button
  • Select proper target connection
  • Confirm debug script and Click “Debug” button
  • Break at main function entry point after launching DS-5 debugger
  • Move to Signal Tap II, set trigger setting and click “Run Analysis F5”
  • Back to DS-5, click “Run” button and see message on Application Console View
  • Move to Signal Tap II and see SPI Signaling


Download

Link to download QuartusII Project File:Soc system.qar 

Link to download the sample application for DS-5 File:How To Debug SPI With SignalTapII.tar.gz


History

December 16, 2015 - Created this page

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‎06-27-2019 04:46 PM
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