How to implement the encoding and decoding operation with 5G Polar Intel® FPGA IP

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How to implement the encoding and decoding operation with 5G Polar Intel® FPGA IP

 

Introduction

This article shows the users how to implement the encoding and decoding operation with 5G Polar Intel® FPGA IP in simulation. It assists users to have a quick start with the latest 5G Polar Intel FPGA IP in Intel® Stratix® 10 FPGA. In the simulation, dummy data is fed into the encoder. The output data from the encoder is converted to LLRs and fed into the decoder to recover back the original data. We will also discuss the configuration, simulation, and result in analysis for better illustration and to facilitate users' understanding.

Software and IP Requirement

• Intel Quartus® Prime version 20.3
• MATLAB* R2020a

 

Theory of Operation

 The following shows the instances used in this article – 5G Polar Encoder, 5G Polar Decoder, test vector, control, and clock generation logic. We will generate example design from the IP and perform customization to facilitate the discussion. The encoder and decoder example designs are generated separately which is indicated by the left and right highlighted boxes.

In the simulation, the test bench read the test vector from a text file and feed it into the encoder. The encoder output is printed in a text file This output will go through manual LLR conversion before being fed into the decoder. The recovered data from the decoder will be checked against the input to the encoder to verify the operation.

Steps of Implementation

1. Generate the example design for the 5G Polar Intel FPGA IP in Decoder mode

 

2. The generated MATLAB simulation folder will consist of the required codes for both encoder and decoder simulation but not the input data for the encoder
3. Repeat the example design generation for the 5G Polar Intel FPGA IP in Encoder mode with the different folder name
4. Copy the polar5g_enc_in.txt and polar5g_enc_out.txt from the Encoder example design to the Decoder example design

5. Open MATLAB and change the working directory to the Matlab folder of the Decoder example design
6. In MATLAB, type make to generate the MEX files

 

7. Type polar5g_codec_tb(4, 2, 4, 1); to execute a test case 

 

8. The first parameter is the list size. The second parameter is the code block length. The third parameter is the CRC type and the last parameter is with/without interleaver.
9. You may refer to the user guide for further details on these parameters and the mapping
10. This test case runs list size = 4, code block length = 64, CRC = CRC16, and the interleaver is on
11. It will execute both the encoder and decoder tests and writes to the data text files
12. Next, we will perform the conversion to LLR codewords
13. Open the polar5g_enc_out.txt which is the encoder output result and change the 0 and 1 to their corresponding strongest LLR codewords to ease the demo. For example, convert the value of 0 to -31 and the value of 1 to 31

 

14. Save the converted LLR codewords to polar5g_dec_in.txt
15. Go back to MATLAB and re-run the same test case
16. Open the polar5g_enc_in.txt and polar5g_dec_out.txt
17. If you compare the input data to Encoder with the Decoder output, you should see matching result

18. The additional 16 bits in red for the Decoder output are the CRC bits

 

Conclusion

This article shows the users how to implement the encoding and decoding operation with 5G Polar Intel FPGA IP in simulation.

References

• 5G Polar Intel® FPGA IP User Guide

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug20308.pdf

Revision History

Date	Version	Author	Changes
June 14, 2021	1.0	Chan, Chee Pin	Initial Release

Notices & Disclaimers 

Intel technologies may require enabled hardware, software or service activation. 
No product or component can be absolutely secure.  
Your costs and results may vary.  
Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.
The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications.  Current characterized errata are available on request.

2021-06-27

Chee Pin Chan