Community
cancel
Showing results for 
Search instead for 
Did you mean: 

IP Migration Guideline for CPRI v5 (ACDS) to CPRI v6 (Webcore)

IP Migration Guideline for CPRI v5 (ACDS) to CPRI v6 (Webcore)


Introduction

This page will guide you on how to migrate from your current Altera CPRI IP (v5) core to the new CPRI IP (v6) webcore.

Installation

CPRI IP v6 Webcore is no longer a ACDS IP, that means it will not be pre-installed with your QuartusII installation. You will need a valid license and SSLC access to download the updated Webcore version for your QuartusII installation. Please see this link for further information.

Parameter

v5 ParameterNameEquivalent v6 ParameterNameFunctional Change/Remark
Operation ModeSYNC_MODESynchronization modeSYNC_MODENo changes
Line RateLINERATELine bit rateBIT_RATENo changes
Receiver FIFO DepthWIDTH_RX_BUFReceiver soft buffer depthWIDTH_RX_BUFNo changes
Transceiver Reference Clock FrequencyXCVR_FREQ--Transmitter and receiver reference clocks are separated as Tx PLL is instantiated out of the IP core, please refer to User Guide on how to connect a Tx PLL. For receiver reference clock, please use CDR_XCVR_FREQ
Enable auto-rate negotiationAUTO_RATEEnable line bit rate auto-negotiationAUTORATENo changes
Include automatic round-trip delay calibrationCALOFF--Feature is depreciated, please refer to section Features
Mapping modesMAP_MODE--Feature is moved to reference design
Number of antenna/carrier interfaceN_MAP--Feature is moved to reference design
Enable MAP interface synchronization with core clockSYNC_MAP--Feature is moved to reference design
Include all control word access through CPUVSSOFFEnable all control word access via management interfaceCTRL_WDNo changes
--Selected device familyDEVICEDefault selected device family in QuartusII project
--Operation modeTRX_MODEAllows duplex or simplex mode
--Transmitter local clock division factorTX_LOCAL_CLK_DIVDivide the high speed clock from Tx PLL, mostly for multiple channels sharing single Tx PLL design
--Number of receiver CDR reference clockCDR_REFCLK_CNTAllows multiple CDR reference clock input, mostly for line bit rate option 7A and 8
--Recovered clock sourceRCVD_CLKAllows clock source from PCS or PMA
--Receiver CDR reference clock frequencyCDR_XCVR_FREQAllows selection of receiver CDR reference clock
--Enable line bit rate auto-negotiation down to 614.4MbpsRATE614Allows removal of 614.4Mbps to simplify clocking scheme
--Management interface standardCPU_IF_MODEAllows different management interface standard
--Avalon-mm interface addressing typeCPU_IF_ADDR_MODESelects word or byte addressing for Avalon-MM interface
--Auxiallary (AUX) and direct interface write latency cycleIF_LATENCYWrite latency (clock cycle) of interface with regards to Radioframe position
--Enable Auxiallary (AUX) interfaceAUX_ENAUX interface for full Radioframe access
--Enable direct Z.130.0 alarm via management interfaceFLSAR_ENDirect interface for Z.130.0 access
--Enable direct ctrl_axc access interfaceCTRL_AXC_ENDirect interface for Ctrl_AxC access
--Enable direct vendor specific interfaceVS_ENDirect interface for Vendor Specific Space access
--Enable direct real-time vendor specific interfaceRTVS_ENDirect interface for Real-time Vendor Specific Space access
--Enable start-up sequence state machineSTARTUP_SEQ_SM_ENL1 Start-up Procedures and transition control
--Enable protocol version and C&M channel setting auto-negotiationNEGO_ENAutomates State C and State D control in L1 start-up procedures
--Enable direct I/Q mapping interfaceIQ_ENDirect interface for to I/Q slot access
--Enable HDLC serial interfaceHDLC_SERIAL_ENAccess to HDLC slot as serial bit, compatible to all PCS variants
--Ethernet PCS InterfaceXMI_IF_ENAllows to choose between MII or GMII, or disable PCS entirely
--Ethernet PCS Tx/Rx buffer depthETH_PCS_BUF_WIDTHSoft buffer depth of Ethernet PCS
--Enable L1 debug interfacesDEBUG_ENExpose debug signals on L1 logic including transceiver status
--Enable transceiver PMA serial forward loopback pathDEBUG_SERIAL_LB_ENEnable register controlled transceiver PMA loopback
--Enable parallel forward loopbak pathsDEBUG_FORWARD_LB_ENEnable register controlled soft IP parallel loopback, without transceiver
--Enable parallel reversed loopback pathsDEBUG_REVERSE_LB_ENEable register controlled soft IP reversed parallel loopback, without transceiver, for slave configuration


Version history
Revision #:
1 of 1
Last update:
‎06-28-2019 05:02 PM
Updated by:
 
Contributors