This component allows you to map up to 31 interrtups into 1. It has three registers.
interrupt enable register( 32 bits R/W) Each bit is the enable for the corresponding interrupt.
pending interrupts. (32 bits R) The raw interrtups masked by the interrupt enable then ORed together.
raw interrupts. (32 bits R) The values of the 32 interrupts comming in. Not masked.
If all the bits in the interrupt enable registers are 0 then the output irq is never asserted, and the pending interrupts will be zero ( because it is the bitwise AND of the raw interrupts and the interrupt enable register all ORed together). The raw interrupts always shows the exact value of the 32 interrupt in lines. ie. IRQ0 is bit 0, IRQ1 is bit 1 etc.
Version 9.1 ( preliminary may change)
Fixes a few minor issue
Now there are 32 interrupts in not just 31
Pending interrupts are just the simple bitwise AND of the raw interrupts and the interrupt enable register. The ORing was a mistake in 9.0.