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- Inferring Stratix V DSP Block in FFT Applications (Verilog HDL)

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Inferring Stratix V DSP Block in FFT Applications (Verilog HDL)

This page describes how to infer the variable precision digital signal processing (DSP) blocks in Stratix® V devices to build complex multipliers in FFT applications.

For more information on how to implement FFTs with 28-nm Variable-Precision DSP Architecture, please refer to

http://www.altera.com/literature/wp/wp-01140-fir-fft-dsp.pdf

This page contains the following complex multipliers to demonstrate Stratix V DSP Block capabilities:

• 18x18 complex multiplier

• 18x25 cpmplex multiplier

• 27x27 complex multiplier

You can download the design files here.

Using the dual 18x18 multipliers in a single DSP block allows a designer to implement an 18x18 bit complex multiply using only two DSP blocks, as shown in Figure 1

18x18 complex multiply

(x+j*y)*(cos+j*sin) = (x*cos-y*sin)+j*(x*sin+y*cos)

You can download the design files here.

For 18-bit twiddle factor with 25-bit data, the complex mulplication can be rearranged as in Eq.1

(x+j*y)*(cos+j*sin) = (x*cos-y*sin) + j*(x*sin+y*cos)

= ((x-y)*cos + (cos-sin)*y) + j*((x+y)*sin + (cos-sin)*y)

By using the 26-bit pre-adder and a 27-bit x 27-bit multiplier available in Stratix V DSP block, the 18x25 complex multiplication can be structured as shown in Figure 3.

Structured this way, an 18x25 complex multiply operation takes only three variable precision blocks.

You can download the design files here.

Using the dual 18x18 multipliers in a single DSP block allows a designer to implement an 18x18 bit complex multiply using only two DSP blocks, as shown in Figure ?

27x27 complex multiply

(x+j*y)*(cos+j*sin) = (x*cos-y*sin)+j*(x*sin+y*cos)

You can download the design files here.

© 2010 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

misleading or inaccurate.

For more complete information about compiler optimizations, see our Optimization Notice.