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Inferring Stratix V DSP Block in FFT Applications (Verilog HDL)

Inferring Stratix V DSP Block in FFT Applications (Verilog HDL)



Introduction

This page describes how to infer the variable precision digital signal processing (DSP) blocks in Stratix® V devices to build complex multipliers in FFT applications.

For more information on how to implement FFTs with 28-nm Variable-Precision DSP Architecture, please refer to 

http://www.altera.com/literature/wp/wp-01140-fir-fft-dsp.pdf


This page contains the following complex multipliers to demonstrate Stratix V DSP Block capabilities:

• 18x18 complex multiplier

• 18x25 cpmplex multiplier 

• 27x27 complex multiplier


You can download the design files here.


18x18 complex multiplier


Using the dual 18x18 multipliers in a single DSP block allows a designer to implement an 18x18 bit complex multiply using only two DSP blocks, as shown in Figure 1 

18x18 complex multiply

(x+j*y)*(cos+j*sin) = (x*cos-y*sin)+j*(x*sin+y*cos)

5/59/Dsp_block5_fft_figure1.JPG ( Dsp block5 fft figure1.JPG - click here to view image )

3/3d/Dsp_block5_fft_figure2.JPG ( Dsp block5 fft figure2.JPG - click here to view image )

You can download the design files here.


18x25 complex multiplier


For 18-bit twiddle factor with 25-bit data, the complex mulplication can be rearranged as in Eq.1

(x+j*y)*(cos+j*sin) = (x*cos-y*sin) + j*(x*sin+y*cos)

= ((x-y)*cos + (cos-sin)*y) + j*((x+y)*sin + (cos-sin)*y)

By using the 26-bit pre-adder and a 27-bit x 27-bit multiplier available in Stratix V DSP block, the 18x25 complex multiplication can be structured as shown in Figure 3.

5/5a/Dsp_block5_fft_figure3.JPG ( Dsp block5 fft figure3.JPG - click here to view image )

Structured this way, an 18x25 complex multiply operation takes only three variable precision blocks.

c/c9/Dsp_block5_fft_figure4.JPG ( Dsp block5 fft figure4.JPG - click here to view image )

You can download the design files here.


27x27 complex multiplier


Using the dual 18x18 multipliers in a single DSP block allows a designer to implement an 18x18 bit complex multiply using only two DSP blocks, as shown in Figure ? 

27x27 complex multiply

(x+j*y)*(cos+j*sin) = (x*cos-y*sin)+j*(x*sin+y*cos)

8/85/Dsp_block5_fft_figure5.JPG ( Dsp block5 fft figure5.JPG - click here to view image )

5/51/Dsp_block5_fft_figure6.JPG ( Dsp block5 fft figure6.JPG - click here to view image )

You can download the design files here.


© 2010 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

misleading or inaccurate.

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Last update:
‎06-27-2019 05:13 PM
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