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The design demonstrates Ethernet operation between the Triple-Speed Ethernet Intel® FPGA IP core and onboard Marvell 88E1111 PHY chip through SGMII. TCL scripts are included to allow users to test the auto-negotiation feature, internal MAC loopback, internal PHY loopback, and TX/RX interop with the external tester at a data rate of 10/100/1000 Mbps. The packet statistics report will be generated as the output result of the internal loopback test.
The design example can be found on the Intel® FPGA Design Store at https://www.intel.com/content/www/us/en/design-example/714770/intel-agilex-7-fpga-triple-speed-ethernet-and-on-board-phy-chip-reference-design.html.
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Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
Per informazioni più complete sulle ottimizzazioni del compilatore, vedere: Avviso di ottimizzazione.