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Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

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Intel FPGA Wiki

The Intel FPGA Wiki has moved!

Welcome to the Intel FPGA Forums (formerly the FPGA Wiki)

This Intel FPGA Wiki was shut off to the public on June 28, 2019 and has since moved to the Intel Forums.

Redirects have been put in place to redirect each wiki page to its new home in the Intel FPGA Forum for the external customer experience. 

To navigate to the new forum pages, go to

·        FPGA Developers à Programmable Devices à Documents

Note: Each page in the “Documents” tab is a replica of its previous Intel FPGA Wiki page.

For tips on how to search for previous wiki pages, please refer to How to Search FPGA Wiki's


If you happen to find asset links or pages on the Intel Forum that need to be cleaned up or have any general questions or concerns, please reach out to, for any forum related issues.

We apologize for any inconvenience caused, and greatly appreciate your assistance to help inform our customers of this migration to Intel forums. We are also working on enhancing the Customer experience in the Forum site, it is expected to evolve over the next few months. 

Version history
Last update:
‎06-26-2019 03:11 PM
Updated by: