Numonyx makes a series of parts in the M18 line which include StartaFlash as well as a PSRAM (Cellular Memory) die. This saves board space and is very energy efficient. Using the AD-MUX option (multiplexing both data and address on the same 16 pins) saves pins on the FPGA with only modest decrease in performance. The dual die part can be run in a totally asynchronous mode which is very slow or in a synchronous mode which improves performance significantly. Flash writes must be asynchronous.
This implementation of a M18 controller has three Avalon slaves; PSRAM, PROG, FLASH.
The PSRAM interface allows the Avalon master to access the PSRAM die. This slave supports pipelined transfers.
The Flash interface allows for READs of the Flash array only. This slave supports pipelined transactions.
The PROG interface is exclusively or programming the flash array. This interface does not support pipelined transfers. It only supports simple Avalon transactions. It views the same die as the Flash slave interface does but at a different offset.
Making the component have these three interfaces simplified the task of writing the controller. The hardware timing requirements on each type of interface are different.
Because the flash is only 16 bit wide, the interface uses the DDR IO cells to run the external interface at twice the rate of the local interface providing a 32 bit local data path. The max frequency is 64Mhz local and 128Mhz phase adjusted clock must be provided to the physical part. Using a dedicated clockout pin and a cyclone III part the PLL phase was 195 degrees.
This component contains only a .tcl file and the associated verilog file. While this interface was written for a very specific part, one should be able to modify it to accommodate other M18 interfaces.
Downloading the component
The psram_flash_component can be place in any of several places.
1-Place the folder psram_flash_component in to the standard components directory
The SOPC_Builder will automatically search for components in any subdirectory under the IP directory. ( do not place it in the Altera subdirectory this one has a fixed mapping)
2-Or you can place it in the ip subdirectory under your current project.
3-You can also place it anywhere else you want but you will need to tell SOPC_Builderthe path. ( Tools/options)
Then next time you launch SOPC builder you will have a new component in the Memories and Memory Controllers
Using the component
The most critical issues with using this component is getting the phase of the clocks the drives the M18 component correct.
There are three clocks.
1- The external clock which goes to the physical M18 device. It should be on a dedicated clock output pin.
All the output register have been locked into the IO cells for maximum speed. The phase shift should be 195 degrees for a 128 Mhz clock.
2- Shift_sci_clk -intput to the sopc_builder component. This take a clock 1/2 the rate of the external clock and shifted by 60 degrees for a 64Mhz clock.
3- SOPC_Builder clock. This is the system clock which is assigned to the component in sopc_builder. It has no phase shift and is 1/2 the rate of the external clock. So 64Mhz in this example.
This component requires Quartus 9.0 or later. 2 additional PLL outputs. One for the M18 at 2x the frequency and one that is phase shifted 60 from the sopc_builder clock.