This paper discusses issues for connecting a local bus for the Power Quick 8349e to the Avalon switch fabric.There are two examples included however they have never been verified so bug may exist. However the interface is fairly simple to implement.
PPC PowerQuick 8439e
The PowerQuick 8439e uses a multiplexed address/data bus. This means that each transaction takes at least two clock cycles. It supports single and burst transactions. The nice thing about the burst is they always go to completion, which is what the Avalon burst signals do.
Most signals map straight across to the Avalon equivalent.
Included is two example interfaces. The first example is the mpc8349e_local_interface.This interface supports bursting from the local bus to the Avalon switch fabric.However this example does not register the signals coming on and off chip.While this interface has the lowest latency the result is a slow Fmax.To speed up this Fmax registering the incoming and outgoing signals is needed like shown in the second example. This interface is for example purposes only and has logic flaws in it.
The second example “freescale_avalon_bridge” is an example interface that has only supports single transactions but is fully registered so that the interface can operate at high clock rates.This interface is very adequate for most applications.Only applications which need the throughput that burst can give need implement the burst logic.
Below is a list of signals and how to translate them.Some of these signals can be made from the GPL pins
This is the combination address/Data bus.It is address when the ALE signal is high and should only be driven by the FPGA when the LOEn is asserted.It is driven by the Readdata[31:0].Remember the LAD is LAD is most significant whereas the Avalon assumesbit 31 is most significant.
This is the address latch enable.This should be the input to a clock enable on a register which will capture address data from the LAD signals.Because the 8439 local interface can only handle one transaction at a time you can register all addresses that the LAD signal conditions.
This can be on of several chip selects. This will be asserted after the LALE signal has loaded an address. This signal must remain active for the entire cycle until LTAn is asserted.
This is the standard r/w signal.It must be ORed or ANDed with LCSn to produce the Avalon Read and Write signal.Asserting the Read and Write on Avalon side initiates a transfer cycle.If you are registering the signals great care must be taken to de-assert and the Read and Write signals for the proper number of cycles after Waitrequest is de-asserted. If this is not done an extra read or write cycle will be inadvertently initiated.A good example of this is the “freescale_avalon_bridge”.
These are the four byte enables.They are only need if the processor plan on writing to memories with accesses less then 32 bit in width.Like the LAD signal the order of these signals must be reversed.It maps to the Avalon BE[3:0] signals.
This signal though not strictly need is a nice simplification.It can be used to determine when to drive the Avalon Readdata signal on the LAD pins.
Tranfer Acnowledge is asserted by the FPGA to terminate and Read or Write cycle.Maps directly to the Waitrequest_n signal.If you are registering the signals care must be take not to assert TA for more than one clock cycle. Note: The Avalon Waitrequest signal can be asserted or de-asserted when there is no transaction pending for this reason registered interfaces must take care to force a de-assertion of TA at the end of a cycle and keep it deasserted until a valid waitrequest is detected.( this means that Read or Write must be active and Waitrequest_n is da-asserted) A good example of this is in the “freescale_avalon_bridge”
LGPLx (Burst indicator)
Any one of the GPL pins can be configured to indicate a burst (See the MPC8439e Ref manual for more details. This signal needs to be configured such that is burst indicator like figure 10-80 shows )The nice thing about burst on this interface is there is not early termination. So when a burst starts it must complete.This is the same way the Avalon bus behaves. The Avalon Burst signals must be set to the value of 1 when a non burst transaction occurs and to 2 or 4 (depending on the length of the burst from the PPC).
Creating interfaces to external processors is not difficult but requires a little care.If you only need a interface to talk to registers in the FPGA the simple interface will do.You can support a slower clock and may not even need to register the signals greatly reducing the complexity of the interface.Adding the registers improves the FMAX performance at the cost of LEs and Latency.Adding Burst capabilities is import if you are moving large amounts of data and need to do it as fast as possible.Other interface options are PCI.Using Altera’s PCI core or one of our partner’s PCI cores you can easily interface to Avalon and take advantage of the SOPC Builder tool.